Networks on Chip: The New Trend of On-Chip Interconnection

Mahanta, Hridoy Jyoti; Biswas, Abhijit; Hussain, Md. Anwar

doi:10.1109/csnt.2014.214

Cited by 10 publications

(13 citation statements)

References 6 publications

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“…In this regard, the bus in SoC has been replaced by a network of routers that controls the communication process among nodes in the established network. Based on this, NoC presents a number of characteristics such as low-latency, high-bandwidth, and scalability [10,11].…”

Section: Network-on-chip Architecturementioning

confidence: 99%

“…Also, this can be achieved using asynchronous or synchronous modes [11]. So, with these topologies, certain routing techniques can be employed for packet routing between nodes [10]. As depicted in Figure 1(c), components such as routers and channels (interconnection links) are required for packet routing [11].…”

Section: Network-on-chip Architecturementioning

confidence: 99%

“…It is noteworthy that some routing techniques are specially intended for NoC. As a result, they are well-designed to be deadlock 1 -free [10].…”

Section: Network-on-chip Architecturementioning

confidence: 99%

“…To address the limitation, various variations such as folded hypercube, dual cube, crossed cube, cube-connected cycles, hierarchical cube, and metacube have been presented. A number of these topologies are depicted in Figure 8 and are mainly focusing on reducing the associated node degree and/or minimizing the network diameter while the diameter is kept as small as possible [10,21,22].…”

Section: Ring Toplogymentioning

confidence: 99%

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Network-on-Chip Topologies: Potentials, Technical Challenges, Recent Advances and Research Direction

Alimi¹,

Patel²,

Aboderin³

et al. 2022

Network-on-Chip - Architecture, Optimization, and Design Explorations

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Integration technology advancement has impacted the System-on-Chip (SoC) in which heterogeneous cores are supported on a single chip. Based on the huge amount of supported heterogeneous cores, efficient communication between the associated processors has to be considered at all levels of the system design to ensure global interconnection. This can be achieved through a design-friendly, flexible, scalable, and high-performance interconnection architecture. It is noteworthy that the interconnections between multiple cores on a chip present a considerable influence on the performance and communication of the chip design regarding the throughput, end-to-end delay, and packets loss ratio. Although hierarchical architectures have addressed the majority of the associated challenges of the traditional interconnection techniques, the main limiting factor is scalability. Network-on-Chip (NoC) has been presented as a scalable and well-structured alternative solution that is capable of addressing communication issues in the on-chip systems. In this context, several NoC topologies have been presented to support various routing techniques and attend to different chip architectural requirements. This book chapter reviews some of the existing NoC topologies and their associated characteristics. Also, application mapping algorithms and some key challenges of NoC are considered.

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Section: Network-on-chip Architecturementioning

confidence: 99%

Section: Network-on-chip Architecturementioning

confidence: 99%

“…It is noteworthy that some routing techniques are specially intended for NoC. As a result, they are well-designed to be deadlock 1 -free [10].…”

Section: Network-on-chip Architecturementioning

confidence: 99%

Section: Ring Toplogymentioning

confidence: 99%

See 2 more Smart Citations

Network-on-Chip Topologies: Potentials, Technical Challenges, Recent Advances and Research Direction

Alimi¹,

Patel²,

Aboderin³

et al. 2022

Network-on-Chip - Architecture, Optimization, and Design Explorations

View full text Add to dashboard Cite

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“…The size of an NoC depends on the number of PEs. So far, thousands of PEs have been integrated on a single chip [Mahanta et al 2014], in which N is about 32. In practical applications, N usually ranges between 4 and 10.…”

Section: Reconfiguration Time and Hardware Overheadmentioning

confidence: 99%

Efficient Fault-Tolerant Topology Reconfiguration Using a Maximum Flow Algorithm

Ren

Liu

Yin

et al. 2015

ACM Trans. Reconfigurable Technol. Syst.

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With an increasing number of processing elements (PEs) integrated on a single chip, fault-tolerant techniques are critical to ensure the reliability of such complex systems. In current reconfigurable architectures, redundant PEs are utilized for fault tolerance. In the presence of faulty PEs, the physical topologies of various chips may be different, so the concept of virtual topology from network embedding problem has been used to alleviate the burden for the operating systems. With limited hardware resources, how to reconfigure a system into the most effective virtual topology such that the maximum repair rate can be reached presents a significant challenge. In this article, a new approach using a maximum flow (MF) algorithm is proposed for an efficient topology reconfiguration in reconfigurable architectures. In this approach, topology reconfiguration is converted into a network flow problem by constructing a directed graph; the solution is then found by using the MF algorithm. This approach optimizes the use of spare PEs with minimal impacts on area, throughput, and delay, and thus it significantly improves the repair rate of faulty PEs. In addition, it achieves a polynomial reconfiguration time. Experimental results show that compared to previous methods, the MF approach increases the probability to repair faulty PEs by up to 50% using the same redundant resources. Compared to a fault-free system, the throughput only decreases by less than 2.5% and latency increases by less than 4%. To consider various types of PEs in a practical application, a cost factor is introduced into the MF algorithm. An enhanced approach using a minimum-cost MF algorithm is further shown to be efficient in the fault-tolerant reconfiguration of heterogeneous reconfigurable architectures. . 2015. Efficient fault-tolerant topology reconfiguration using a maximum flow algorithm.

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