Neural Acceleration for General-Purpose Approximate Programs

Abstract

This paper describes a learning-based approach to the acceleration of approximate programs. We describe the Parrot transformation, a program transformation that selects and trains a neural network to mimic a region of imperative code. After the learning phase, the compiler replaces the original code with an invocation of a low-power accelerator called a neural processing unit (NPU). The NPU is tightly coupled to the processor pipeline to accelerate small code regions. Since neural networks produce inherently approximate results, we define a programming model that allows programmers to identify approximable code regions-code that can produce imprecise but acceptable results. Offloading approximable code regions to NPUs is faster and more energy efficient than executing the original code. For a set of diverse applications, NPU acceleration provides wholeapplication speedup of 2.3× and energy savings of 3.0× on average with quality loss of at most 9.6%.

Aladdin: A pre-RTL, power-performance accelerator simulator enabling large design space exploration of customized architectures

“…We perform rigorous validation of Aladdin against handwritten RTL implementations and a commercial HLS design flow. We show that Aladdin can model the behavior of recently published accelerators [38,55,19] and typical accelerator kernels [17] (Section 4). 3.…”

“…Hardware acceleration exists in many forms, such as analog accelerators [6,50], static [13,19,28,38,43,52,55] and dynamic datapath accelerators [14,25,27], and programmable accelerators, such as GPUs and DSPs. In this work, we focus on static datapath accelerators.…”

“…Starting with an unconstrained program DDDG, which corresponds to an initial representation of accelerator hardware, Aladdin applies optimizations as well as constraints to the graph to create a realistic model of accelerator activity. We rigorously validated Aladdin against RTL implementations of accelerators from both handwritten Verilog and a commercial HLS tool for a range of applications, including accelerators in Memcached [38], HARP [55], NPU [19], and a commonly used throughput-oriented benchmark suite, SHOC [17]. Our results show that Aladdin can model performance within 0.9%, power within 4.9%, and area within 6.6% compared to accelerator designs generated by traditional RTL flows.…”

Design and Application Space Exploration of a Domain-Specific Accelerator System

“…Like most of the standalone accelerators [15][16][17], the accelerator in the proposed system-called reconfigurable application specified processor (RASP), is a loosely coupled configurable engine attached to the AXI bus. Data communication between on-chip memory and external storage, i.e., DDR3 is provided through direct memory access (DMA) in the RASP.…”

Hardware acceleration for neuromorphic computing: An evolving view

“…Examples include neural network accelerators for signal processing [3], digital approximate computing accelerators that leverage neural network algorithms [4], and heterogeneous systems built with GPUs and CPUs for deep learning accelerations [5]. However, traditional CMOS technology has scaling limitations for neuromorphic system design, as many transistors are usually required to build one neuron [5].…”