Neuro chips with on-chip back-propagation and/or Hebbian learning

Shima, Takeshi; Kimura, Taiki; Kamatani, Y.; Itakura, Tetsuro; Fujita, Yasuhiko; Iida, Takuya

doi:10.1109/4.173117

Cited by 68 publications

(8 citation statements)

References 18 publications

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“…Categorized by storage types, there are five kinds of synapse circuits: capacitor only [1], [7]- [11], capacitor with refreshment [12]- [14], capacitor with EEPROM [4], digital [15], [16], and mixed D/A [17] circuits.…”

Section: B Synapse Circuitsmentioning

confidence: 99%

A CMOS feedforward neural-network chip with on-chip parallel learning for oscillation cancellation

Liu

Brooke

Hirotsu

2002

IEEE Trans. Neural Netw.

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Abstract-This paper presents a mixed signal CMOS feedforward neural-network chip with on-chip error-reduction hardware for real-time adaptation. The chip has compact on-chip weighs capable of high-speed parallel learning; the implemented learning algorithm is a genetic random search algorithm-the random weight change (RWC) algorithm. The algorithm does not require a known desired neural-network output for error calculation and is suitable for direct feedback control. With hardware experiments, we demonstrate that the RWC chip, as a direct feedback controller, successfully suppresses unstable oscillations modeling combustion engine instability in real time.Index Terms-Analog finite impulse response (FIR) filter, direct feedback control, neural-network chip, parallel on-chip learning, oscillation cancellation.

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Section: B Synapse Circuitsmentioning

confidence: 99%

A CMOS feedforward neural-network chip with on-chip parallel learning for oscillation cancellation

Liu

Brooke

Hirotsu

2002

IEEE Trans. Neural Netw.

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“…Thus and can be achieved by suitably decreasing the channelwidth of the input PMOS devices. Using this method, the entire equation of the approximate neuron differentiation can be written as for for (15) where is a constant. The circuit to implement (15) is shown in Fig.…”

Section: A Calculation Blockmentioning

confidence: 99%

“…3(a) is positive so that is low, the voltages of and are sent to the subtractor and the function can be realized. If the signal from the neuron circuit is high for a negative , the capacitors and are discharged and the subtractor output voltage is zero as in (15). Therefore, the function for can be realized.…”

Section: A Calculation Blockmentioning

confidence: 99%

Realization of the CMOS pulsewidth-modulation (PWM) neural network with on-chip learning

Bor

1998

IEEE Trans. Circuits Syst. II

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In this paper, a CMOS very large scale integration (VLSI) design of the pulsewidth-modulation (PWM) neural network with both retrieving and on-chip leaning functions is proposed. In the developed PWM neural system, the input and output signals of the neural network are represented by PWM signals whereas the multiplication and summation functions are realized by using the PWM technique and simple mixed-mode circuits. Therefore, the designed neural network only occupies the small chip area. After compensating the nonideal effects of the switches, the designed circuits have good linearity and large dynamic range. This makes the implementation of onchip learning feasible. To demonstrate the learning capability of the realized PWM neural network, the delta learning rule is realized. An experimental chip with two neurons, twelve synapses, and the associated learning circuits has been fabricated in 0.8m CMOS double-poly double-metal process. The chip area, including the pads, is 3.45 mm 2 3.45 mm. From the measured results, the linearity of synapses versus weight voltages and input pulsewidths can almost be kept under 61% and 60.2%, respectively. The measured results on the three learning examples on AND function, OR function, and simple Chinese word speech classification have successfully verified the function correctness and performance of the designed neural network. Index Terms-Mixed-mode circuit, neural network, pulsewidth modulation (PWM).

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“…The learning algorithm for our ANN could be Hebbian learning [21] or a back-propagation learning scheme [22,11,23], for instance (for complete architectures see these references).…”

Section: The Learning Schemementioning

confidence: 99%

Mixed analog/digital matrix-vector multiplier for neural network synapses

Lehmann

Bruun

Dietrich

1996

Analog Integr Circ Sig Process

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In this work we present a hardware efficient matrix-vector multiplier architecture for artificial neural networks with digitally stored synapse strengths. We present a novel technique for manipulating bipolar inputs based on an analog two's complements method and an accurate current rectifier/sign detector. Measurements on a CMOS test chip are presented and validates the techniques. Further, we propose to use an analog extension, based on a simple capacitive storage, for enhancing weight resolution during learning. It is shown that the implementation of Hebbian learning and back-propagation learning in this system is possible using very little additional hardware compared to the recall mode system.

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Neuro chips with on-chip back-propagation and/or Hebbian learning

Cited by 68 publications

References 18 publications

A CMOS feedforward neural-network chip with on-chip parallel learning for oscillation cancellation

A CMOS feedforward neural-network chip with on-chip parallel learning for oscillation cancellation

Realization of the CMOS pulsewidth-modulation (PWM) neural network with on-chip learning

Mixed analog/digital matrix-vector multiplier for neural network synapses

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