Neuromorphic algorithms on clusters of PlayStation 3s

Taha, Tarek M.; Yalamanchili, Pavan; Bhuiyan, Mohammad A.; Jalasutram, Rommel; Chen, Chong; Linderman, Richard

doi:10.1109/ijcnn.2010.5596751

Cited by 7 publications

(3 citation statements)

References 21 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…A range of neural network emulation projects are underway around the world that include GPU, FPGA, CMP, and ASIC based systems [8][9][10][11][12][13]. In [8,9], the authors demonstrate GPU acceleration of spiking neural models.…”

Section: Related Workmentioning

confidence: 99%

See 1 more Smart Citation

Routing bandwidth model for feed forward neural networks on multicore neuromorphic architectures

Hasan

Taha

2013

The 2013 International Joint Conference on Neural Networks (IJCNN)

Self Cite

View full text Add to dashboard Cite

Specialized multi-core architectures can provide significant speedups for neural network applications. In this study, we examined the on-chip routing network bandwidth requirements for such architectures processing large multilayered feed forward neural networks in a pipelined manner. Two on-chip routing network topologies were examined: mesh networks and hybrid bus-mesh networks. Two routing bandwidth models were developed for each network topology: one examined sending neuron outputs from one layer to the next, while the other examined the streaming of synaptic weights from off-chip memory. The model was validated through several simulations studies. For both mesh and busmesh interconnection area and power of the on-chip routing network was estimated using the Orion on-chip network tool. Our results show that in multi-core neuromorphic architectures, a bus-mesh interconnection requires less routing area and power compared to a mesh interconnection. We also observed that the accumulated bandwidth requirement in the on-chip network to access off-chip data is much greater than bandwidth required to send neuron outputs between cores.

show abstract

Section: Related Workmentioning

confidence: 99%

“…In [8,9], the authors demonstrate GPU acceleration of spiking neural models. Acceleration on high performance clusters [10] and FPGAs [11] are also studied. Since GPU and FPGA systems are relatively high power and area consuming, they are not favorable for embedded applications.…”

Section: Related Workmentioning

confidence: 99%

Routing bandwidth model for feed forward neural networks on multicore neuromorphic architectures

Hasan

Taha

2013

The 2013 International Joint Conference on Neural Networks (IJCNN)

Self Cite

View full text Add to dashboard Cite

show abstract

“…Whilst Taha et al [19] used a cluster of Sony PlayStation 3s (each containing an STI CELL processor) rather than GPUs.…”

Section: Neural Networkmentioning

confidence: 99%

Graphics processing units and genetic programming: an overview

Langdon

2011

Soft Comput

View full text Add to dashboard Cite

A top end graphics card (GPU) plus a suitable SIMD interpreter, can deliver a several hundred fold speed up, yet cost less than the computer holding it. We give highlights of AI and computational intelligence applications in the new field of general purpose computing on graphics hardware (GPGPU). In particular we survey genetic programming (GP) use with GPU. We give several applications from Bioinformatics and show how the fastest GP is based on an interpreter rather than compilation. Finally using GP to generate GPU CUDA kernel C++ code is sketched.

show abstract