Neuromorphic microelectronics from devices to hardware systems and applications

Schmid, Alexandre

doi:10.1587/nolta.7.468

Cited by 10 publications

(6 citation statements)

References 143 publications

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“…Fully exploiting the coding and computation capabilities of biological brains requires the adequacy of the corresponding hardware platform to the peculiarities of the algorithm at different levels: from signal coding up to high level architectures. At the architectural level, the intrinsic parallelism of neural networks lends to the development of neuromorphic custom parallel hardware resembling the architecture of the biological brain to emulate its computing capabilities [62,69,70]. Furthermore, at the signal level, SNNs are better suited than ANNs for hardware implementation, as neurons are active only when they receive an input spike, reducing power consumption and simplifying computation.…”

Section: Cmos Neuromorphic Systemsmentioning

confidence: 99%

Neuromorphic Spiking Neural Networks and Their Memristor-CMOS Hardware Implementations

2019

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Inspired by biology, neuromorphic systems have been trying to emulate the human brain for decades, taking advantage of its massive parallelism and sparse information coding. Recently, several large-scale hardware projects have demonstrated the outstanding capabilities of this paradigm for applications related to sensory information processing. These systems allow for the implementation of massive neural networks with millions of neurons and billions of synapses. However, the realization of learning strategies in these systems consumes an important proportion of resources in terms of area and power. The recent development of nanoscale memristors that can be integrated with Complementary Metal–Oxide–Semiconductor (CMOS) technology opens a very promising solution to emulate the behavior of biological synapses. Therefore, hybrid memristor-CMOS approaches have been proposed to implement large-scale neural networks with learning capabilities, offering a scalable and lower-cost alternative to existing CMOS systems.

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Section: Cmos Neuromorphic Systemsmentioning

confidence: 99%

Neuromorphic Spiking Neural Networks and Their Memristor-CMOS Hardware Implementations

2019

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“…It goes without saying that most conventional modeling and implementation methods of neuromorphic circuits have been based on the first, the second, and the third methods [18][19][20][21][22][23][24][25][26][27][28][29][30]. On the other hand, our group and a few other groups have designed neuromorphic circuits based on the fourth method [31][32][33][34][35][36][37][38].…”

Section: Introductionmentioning

confidence: 97%

A novel ergodic discrete difference equation multi-compartment neuron model: various dendritic phenomena and on-chip differential conditioning

Takeda,

Ishikawa,

Torikai

2024

NOLTA

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A novel membrane potential model whose nonlinear dynamics is described by an ergodic discrete difference equation is presented. It is shown that the model can exhibit various neuron-like behaviors depending on parameter values. Using the ergodic membrane potential model, a novel multi-compartment neuron model (soma-dendrite-synapse model) is presented. It is shown that the model can exhibit various dendritic phenomena depending on parameter values. Based on detailed analyses of the dendritic phenomena, a design procedure of the multi-compartment neuron model to realize conditioning functions is proposed. Furthermore, the neuron model is implemented by a field programmable gate array and experiments validate its conditioning functions. It is then shown that the proposed neuron model consumes much fewer hardware resources and much lower power than a typical conventional multi-compartment neuron model.

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“…Furthermore, the interest in AI computing, which includes neural networks, has also increased [1][2][3][4][5][6]. The neural network is the set of transmissions of signals between numerous calculating units and memories through entangled connections, similarly to how the brain works with spikes, neurons, and synapses [7][8][9][10][11][12]. Due to this feature, conventional computing technology with CPUs is inadequate to carry out the computation for AI [13,14].…”

Section: Introductionmentioning

confidence: 99%

Intellino: Processor for Embedded Artificial Intelligence

et al. 2020

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The development of computation technology and artificial intelligence (AI) field brings about AI to be applied to various system. In addition, the research on hardware-based AI processors leads to the minimization of AI devices. By adapting the AI device to the edge of internet of things (IoT), the system can perform AI operation promptly on the edge and reduce the workload of the system core. As the edge is influenced by the characteristics of the embedded system, implementing hardware which operates with low power in restricted resources on a processor is necessary. In this paper, we propose the intellino, a processor for embedded artificial intelligence. Intellino ensures low power operation based on optimized AI algorithms and reduces the workload of the system core through the hardware implementation of a neural network. In addition, intellino’s dedicated protocol helps the embedded system to enhance the performance. We measure intellino performance, achieving over 95% accuracy, and verify our proposal with an field programmable gate array (FPGA) prototyping.

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Neuromorphic microelectronics from devices to hardware systems and applications

Cited by 10 publications

References 143 publications

Neuromorphic Spiking Neural Networks and Their Memristor-CMOS Hardware Implementations

Neuromorphic Spiking Neural Networks and Their Memristor-CMOS Hardware Implementations

A novel ergodic discrete difference equation multi-compartment neuron model: various dendritic phenomena and on-chip differential conditioning

Intellino: Processor for Embedded Artificial Intelligence

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