Neuromorphic Spiking Neural Networks and Their Memristor-CMOS Hardware Implementations

Abstract

Inspired by biology, neuromorphic systems have been trying to emulate the human brain for decades, taking advantage of its massive parallelism and sparse information coding. Recently, several large-scale hardware projects have demonstrated the outstanding capabilities of this paradigm for applications related to sensory information processing. These systems allow for the implementation of massive neural networks with millions of neurons and billions of synapses. However, the realization of learning strategies in these systems consumes an important proportion of resources in terms of area and power. The recent development of nanoscale memristors that can be integrated with Complementary Metal–Oxide–Semiconductor (CMOS) technology opens a very promising solution to emulate the behavior of biological synapses. Therefore, hybrid memristor-CMOS approaches have been proposed to implement large-scale neural networks with learning capabilities, offering a scalable and lower-cost alternative to existing CMOS systems.

Event-Based Vision: A Survey

“…The following processors (Table 4) have the most mature developer workflows, combined with the widest availability of standalone systems. More details are given in [229], [230].…”

Emerging Materials for Neuromorphic Devices and Systems

“…Each layer needs time to wait to perform the computation until the output of the previous layer is processed; this sequential process can lead to a recognition delay in the neural networks. SNNs have the advantage that they can process data in continuous time by firing spikes that show certain spatiotemporal correlations ( Camuñas-Mesa et al., 2019 ); this is an advantage over sequential processing in DNNs.…”

“…One main issue is the lack of efficient training algorithms and well-established datasets. For DNNs, the availability of numerous datasets has enabled training of a complex deep learning process based on backpropagation learning algorithms ( Camuñas-Mesa et al., 2019 ). However, the training algorithms for DNNs are not directly used for SNNs ( Tang et al., 2019 ).…”

A Low-Power Spiking Neural Network Chip Based on a Compact LIF Neuron and Binary Exponential Charge Injector Synapse Circuits

“…The choice of neural network on chip for this work is SNN, regarded as the third-generation neural network, due to its biological feats and efficiency in the spatial–temporal signal coding [ 28 ]. In SNN, a web is weaved by the interconnections of neurons and synapses to perform inference and training tasks.…”