Neutralization of the Effect of Hardware Trojan in SCADA System Using Selectively Placed TMR

Gunti, Nagendra Babu; Lingasubramanian, Karthikeyan

doi:10.1109/inis.2017.30

Cited by 2 publications

(4 citation statements)

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“…There are two main advantages in comparison with other neutralization techniques that use TMR ( [4] and [5]): resource savings and the use of approximations itself. On the one hand, the area reduction achieved with this technique can suppose an important cost-saving in complex circuits and makes easier to detect HTs by using side-channel techniques.…”

Section: Discussionmentioning

confidence: 99%

“…The use of TMR to thwart HT insertion has been proposed in [10], [4], [5] by N. Gunti et al In such a TMR based method, an HT has to be introduced in at least two copies in order not to be blocked by the majority voter. Authors claim that such duplication of a potential HT makes it relatively big, therefore also relatively easy to detect through side-channel based techniques.…”

Section: B Ht Prevention Methods Based On Redundancymentioning

confidence: 99%

“…As in other similar works that use TMR as neutralization method [10], [4], [5], we have selected the ISCAS'85 benchmarks as target circuits [12]. We have selected two circuits -c499 and c7552 -based on their different sizes and functionalities, to carry out a thoroughly study about the proposed approach.…”

Section: A Methodologymentioning

confidence: 99%

“…The use of DMR and TMR to thwart HTs has been introduced in [3], [4], [5]. However, straightforward replication is not considered as an obstacle to insert an HT in these ICs.…”

Section: Introductionmentioning

confidence: 99%

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Using Approximate Circuits Against Hardware Trojans

et al. 2023

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Hardware Trojans (HTs) are malicious alterations in Integrated Circuits (ICs) that pose an important threat to safety-critical systems. Many techniques based on logic testing or side-channel analysis have been proposed in the literature aiming at detecting such malicious modifications in fabricated ICs. The detection of HTs is becoming more challenging with the shrinking of the technology and the impact of process variations. Therefore there is a need to neutralize the effect of HTs when the typical detection mechanism fails. In this work, we propose to tackle the effect of HTs by leveraging fault-tolerant techniques like Triple Modular Redundancy (TMR). More specifically, we propose to use an approximate TMR in order to neutralize the effects of HTs while saving area and increasing the complexity of inserting HTs. The efficiency of the proposed approach has been evaluated by using the ISCAS'85 benchmarks and stealthy ad-hoc HTs.

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Section: Discussionmentioning

confidence: 99%

Section: B Ht Prevention Methods Based On Redundancymentioning

confidence: 99%

Section: A Methodologymentioning

confidence: 99%

“…The use of DMR and TMR to thwart HTs has been introduced in [3], [4], [5]. However, straightforward replication is not considered as an obstacle to insert an HT in these ICs.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations