Reliability and low power consumption are two major design objectives in today's embedded systems. Since floating-point units (FPU) are required for some embedded applications (e.g., multimedia applications), careful considerations should be given to the reliability and power consumptions of FPUs used in embedded systems. When using existing fault handling mechanisms for FPUs, it has been observed that the division operation imposes a considerable hardware overhead as compared to the addition, subtraction, and multiplication operations. Although the division operation is less frequently used, in reliable applications it is a must that all the components operate properly. In this paper, we present a low power error detection mechanism for the division operation in FPUs. In this technique the FPU multiplier circuitry is modified so that it can be used to detect the errors that may happen in the divider circuitry. The experimental results show that while the proposed technique can detect almost all the errors in the division circuitry, its power-delay-product (PDP) is about 23% lower than that of the traditional error detection techniques.

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