New approach for the assessment of the effect of plasma induced damage on MOS devices and subsequent design manual rules

Abstract

This paper develops a completely new approach for the definition of PID design rules which are relevant for IC design and also test structure layout. The required stress and measurement sequences for the assessment of PID effects and investigation of the design rules on the various geometries of MOS devices are described and discussed. The overall IC yield can be improved when some additional measures are considered and included in the product design.

On the impact of the layout of MOSFET test-structures on NBTI-, PBTI- and HCS-lifetime due to PID

“…Fig. 9 shows an example for extremely different lifetime extrapolations based on data with and without PID [18]. Data of other publication confirms this.…”

“…Reliability device stress can manifest any data, any lifetime extrapolation model when PID is present[18].…”