New architecture for high data rate turbo decoding of product codes

Abstract

This paper presents a new circuit architecture for turbo decoding, which achieves very high data rates when using product codes as error correcting codes. Although this architecture is independent of the elementary code (convolutional or block) used and of the corresponding decoding algorithms, we focus here on the case of product codes. This innovative circuit architecture stores several data at the same address and performs parallel decoding to increase the data rate. It is able to process several data simultaneously with one memory (classkal designs require m memories); its latency decreases when the amount of data processed simultaneously is large. We present results on block turbo decoder designs of 2data, 4-data and 8-data decoders (where 2, 4 and 8 are the number of data symbols processed simultaneously). For each decoder circuit, the latency is decreased, the area of the processing uni! is increased by a factor m and the critical path and memory si�e are constant (the data rate is increased by m 2 if we have m parallel decoders).

Turbo Product Code Decoder Without Interleaving Resource: From Parallelism Exploration to High Efficiency Architecture

“…is the hardware complexity of a SISO decoder with a symbol parallelism equals to p. In [20], this inequality has been verified by synthesis for P sym = {1; 2; 4; 8} for a BCH(32, 26) 2 TPC decoder. In this paper, we propose to verify this inequality for the same code and for P sym = n = 32.…”

“…data transmission over Passive Optical Networks). For a fair comparison, architectures described in [11,[18][19][20] were synthesized with the same technology: ST Microelectronics, CMOS 90 nm with a target frequency f max = 500 MHz. For the remaining architectures, we gathered information from the published papers and technical reports.…”

“…For the same reason, the TPC decoder with multiaccess data [20] has a low efficiency and also requires the use of frame parallelism to achieve 10 Gb/s.…”

“…Increasing P sym also means that the interleaving memory should be able to read/write more than one data during the same clock cycle. Solutions were provided in [20] to exploit this parallelism while avoiding interleaving memory duplication. Synthesis results confirm that the efficiency increases with P sym .…”

“…Moreover, in [20] an architecture that uses symbol parallelism in conjunction with sub-block parallelism, was proposed. The idea is to store several product code matrix symbols at the same address and to design elementary decoders able to process P sym = m symbols during the same clock period (denoted as m-decoders).…”