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This paper presents a new circuit architecture for turbo decoding, which achieves very high data rates when using product codes as error correcting codes. Although this architecture is independent of the elementary code (convolutional or block) used and of the corresponding decoding algorithms, we focus here on the case of product codes. This innovative circuit architecture stores several data at the same address and performs parallel decoding to increase the data rate. It is able to process several data simultaneously with one memory (classkal designs require m memories); its latency decreases when the amount of data processed simultaneously is large. We present results on block turbo decoder designs of 2data, 4-data and 8-data decoders (where 2, 4 and 8 are the number of data symbols processed simultaneously). For each decoder circuit, the latency is decreased, the area of the processing uni! is increased by a factor m and the critical path and memory si�e are constant (the data rate is increased by m 2 if we have m parallel decoders).

International audienceA full-parallel architecture for turbo decoding, which achieves ultra high data rates when using product codes as error correcting codes, is proposed. This architecture is able to decode product codes using binary BCH or m-ary Reed Solomon component codes. The major advantage of our architecture is that it enables the memory blocks between all half-iterations to be removed. Moreover, the latency of the turbo decoder is strongly reduced. In fact, the proposed architecture opens the way to numerous applications such as optical transmission and data storage. In particular, our block turbo decoding architecture can support optical transmission at data rates above 10 Gb/s

International audienceThis article presents an innovative turbo product code (TPC) decoder architecture without any interleaving resource. This architecture includes a full-parallel SISO decoder able to process n symbols in one clock period. Syntheses show the better efficiency of such an architecture compared with existing previous solutions. Considering a 6-iteration turbo decoder of a (32,26)2 BCH product code, synthetized in a 90 nm CMOS technology, the resulting information throughput is 2.5 Gb/s with an area of 233 Kgates. Finally a second architecture enhancing parallelism rate is described. The information throughput is 33.7 Gb/s while an area estimation gives A=10 mum2