New barrier layer design for the fabrication of gallium nitride-metal-insulator-semiconductor-high electron mobility transistor normally-off transistor

Abstract

This paper reports on the fabrication of an enhancement-mode AlGaN/GaN metal-insulator-semiconductor-high electron mobility transistor with a new barrier epi-layer design based on double Al0.2Ga0.8N barrier layers separated by a thin GaN layer. Normally-off transistors are achieved with good performances by using digital etching (DE) process for the gate recess. The gate insulator is deposited using two technics: plasma enhance chemical vapour deposition (sample A) and atomic layer deposition (sample B). Indeed, the two devices present a threshold voltage (V th) of +0.4 V and +0.9 V respectively with ΔV th about 0.1 V and 0.05 V extracted from the hysteresis gate capacitance measurement, a gate leakage current below 2 × 10−10 A mm−1, an I ON/I OFF about 108 and a breakdown voltage of V BR = 150 V and 200 V respectively with 1.5 µm thick buffer layer. All these results are indicating a good barrier surface quality after the gate recess. The DE mechanism is based on chemical dissolution of oxides formed during the first step of DE. Consequently, the process is relatively soft with very low induced physical damages at the barrier layer surface.

Control of V th of the enhancement high-frequency AlGaN/GaN HEMT fabricated by oxygen-based digital etching

“…The second step is oxide etching by hydrochloric acid (HCl) solution or dry BCl 3 plasma etching. [22][23][24][25][26][27][28][29] It was reported that the digital etching depth per cycle is self-limiting and depends primarily on the oxidation depth with different plasma power and time settings. 23) Therefore, the gate recess etching depth can be controlled strictly by the etching cycles.…”