2009
DOI: 10.1016/j.microrel.2008.11.007
|View full text |Cite
|
Sign up to set email alerts
|

New concepts of worst-case delay and yield estimation in asynchronous VLSI circuits

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
1
1

Citation Types

0
2
0

Year Published

2009
2009
2019
2019

Publication Types

Select...
2
1
1

Relationship

0
4

Authors

Journals

citations
Cited by 4 publications
(2 citation statements)
references
References 16 publications
0
2
0
Order By: Relevance
“…Using the data from [9], we have performed a simulation based timing analysis [10,11,12] in VHDL by Aldecs Active-HDL. In this analysis, a suitable extension of the logic simulation process enables all the worst case delays for all the paths in one digital circuit to be obtained with only one run of the simulator.…”
Section: Performance Analysismentioning
confidence: 99%
“…Using the data from [9], we have performed a simulation based timing analysis [10,11,12] in VHDL by Aldecs Active-HDL. In this analysis, a suitable extension of the logic simulation process enables all the worst case delays for all the paths in one digital circuit to be obtained with only one run of the simulator.…”
Section: Performance Analysismentioning
confidence: 99%
“…That is, determining the delays of the paths in a particular asynchronous circuit. Early evaluation of the path delays in the circuit helps avoiding early timing problems as well as circuit performance characterization (Sokolovic, Litovski & Zwolinski 2009). Precise paths delays, of course, can be estimated only in the final steps of the design process.…”
Section: Introductionmentioning
confidence: 99%