2014
DOI: 10.1016/j.vlsi.2013.03.001
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New efficient bit-parallel polynomial basis multiplier for special pentanomials

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Cited by 12 publications
(17 citation statements)
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“…More specifically, among the type II irreducible pentanomials existent in , there are 477 and 1162 different combinations of for which the proposed multiplier has equal and less delay, respectively, than the multiplier in [9]. With respect to area complexity, it was found that the proposed multiplier presents equal number of AND gates in comparison with the other similar multipliers existing in the literature (except for the approach presented in [21]) and a higher number of XOR gates in comparison with the other multipliers. This increased number of XOR gates is due to the separation of the monolithic functions into the corresponding terms in order to achieve a reduced delay for multiplication.…”
Section: ) Time Complexitymentioning
confidence: 87%
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“…More specifically, among the type II irreducible pentanomials existent in , there are 477 and 1162 different combinations of for which the proposed multiplier has equal and less delay, respectively, than the multiplier in [9]. With respect to area complexity, it was found that the proposed multiplier presents equal number of AND gates in comparison with the other similar multipliers existing in the literature (except for the approach presented in [21]) and a higher number of XOR gates in comparison with the other multipliers. This increased number of XOR gates is due to the separation of the monolithic functions into the corresponding terms in order to achieve a reduced delay for multiplication.…”
Section: ) Time Complexitymentioning
confidence: 87%
“…All these works exploit subexpression sharing in order to find efficient architectures. Other methods use the divide-and-conquer approach for polynomial multiplication in order to reduce the complexity of the multiplier [19], [21]. In [9], a new PB multiplication method was used.…”
mentioning
confidence: 99%
“…We observed that when substitute (18) into (19), each t i is the sum of at most m 2 terms. Plus the delay of computing u i v j , the circuit delay for parallel implementation of (19) is at most T A þ ⌈log 2 ð m 2 Þ⌉T X .…”
Section: #Andmentioning
confidence: 94%
“…Recently, Park et al [18] proposed a new divide and conquer approach for odd degree polynomial multiplication. This approach is analogous to Karatsuba algorithm but divides a polynomial according to exponent parity of the indeterminate.…”
Section: The Pchs Algorithmmentioning
confidence: 99%
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