New insights on bottom layer thermal stability and laser annealing promises for high performance 3D VLSI

Abstract

For the first time the maximum thermal budget of in-situ doped source/drain State Of The Art (SOTA) FDSOI bottom MOSFET transistors is quantified to ensure transistors stability in Sequential 3D (CoolCube TM ) integration. We highlight no degradation of Ion/Ioff trade-off up to 550°C. Thanks to both metal gate work-function stability especially on short devices and silicide stability improvement, the top MOSFET temperature could be relaxed up to 500°C. Laser anneal is then considered as a promising candidate for junctions activation. Based on in-depth morphological and electrical characterizations it demonstrates very promising results for high performance Sequential 3D integration.

FDSOI bottom MOSFETs stability versus top transistor thermal budget featuring 3D monolithic integration

“…To ensure a local thermal budget of the bottom MOSFET in this 400-500°C range alternative thermal processing like laser annealing [11,12] could be envisaged to perform dopant activation. Indeed, Laser anneal thanks to its low in-depth thermal diffusion is a promising opportunity for top transistor dopant activation: it is expected to provide high activation together with surface confined heating [13]. For example an Excimer (wavelength: 308 nm, pulse duration: $200 ns) as presented in [13] could be used.…”

“…Indeed, Laser anneal thanks to its low in-depth thermal diffusion is a promising opportunity for top transistor dopant activation: it is expected to provide high activation together with surface confined heating [13]. For example an Excimer (wavelength: 308 nm, pulse duration: $200 ns) as presented in [13] could be used. To overcome dopant deactivation one solution consists in using a single type of dopant As or P with a reduced implantation dose as proposed in [14].…”

3d Vlsi

“…In Section 2, we described that the main challenge for sequential F2B is to achieve high-performance transistors across all tiers within a low-thermal fabrication process. However, we have to point out that despite technical challenges, promising solutions are under development as was recently presented [3].…”

“…This implies that the performance of the top tier may not be the same as that of the bottom tier. Recently, [3] quantifies the maximum thermal budget of in-situ doped source / drain fully depleted silicon-on-insulator (FDSOI) MOSFET transistors to ensure transistor stability in sequential F2B integration. Due to silicide stabil- ity improvement, the top MOSFET temperature could be relaxed up to 500 • .…”

Monolithic 3-D FPGAs

“…Amorphous or polycrystalline TFTs are easy to fabricate and can be integrated onto CMOS wafers at temperature below 400 C. There are also research efforts to stack single-crystal silicon film for transistor fabrication on top of silicon CMOS circuits. It has been shown that the top silicon transistor process temperature can be relaxed down to 500 C without degrading the bottom silicon transistors' performance and promising results have been obtained with laser annealing for junction activation [23]. However, the relatively small throughput of laser annealing would be a concern.…”