New Low Glitch and Low Power DET Flip-Flops Using Multiple C-Elements

Lapshev, Stepan; Hasan, S. M. Rezaul

doi:10.1109/tcsi.2016.2587282

Cited by 23 publications

(20 citation statements)

References 13 publications

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“…To reduce the input loading, the two structures are merged to share transistors connected with the data input. e proposed glitch-free novel dual edge triggered flip-flop has the lowest power consumption and lowest power delay product (PDP) as compared to the existing dual edge triggered flip-flop designs [10][11][12]. e proposed design has the smallest number of transistors and consequently occupies a small area and has the lowest propagation delay, thus providing high speed and high efficiency.…”

Section: Resultsmentioning

confidence: 99%

“…Bonetti et al [11] proposed a dual edge triggered ip-op, as shown in Figure 2, to overcome the built-in clock overlap threat, by using true single-phase clock circuits instead of an inverted clock and clarify the issue of clock overlapping by using the TSPC circuits and an internal dual feedback structure. Figure 3 shows the LG_C circuit design [12] which improved with common Latch MUX dual edge triggered ipops; because of this fact, ip-ops internal circuit node value never changes with the changes in the input value. e LG_C circuit design presented improvement in the energy dissipation.…”

Section: Existing Designsmentioning

confidence: 99%

“…We have designed a low-power glitch-free novel dual edge triggered ip-op circuit design, as shown in Figure 5. Existing DET-FF designs [10][11][12] are designed by using only the C-element circuits. In the proposed design, we have used 2P-1N three-transistor structure with the combination of C-element circuit.…”

Section: Proposed Novel Det-ffmentioning

confidence: 99%

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A Glitch-Free Novel DET-FF in 22 nm CMOS for Low-Power Application

Singar

Joshi

Ghosh

2018

Journal of Nanotechnology

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Dual edge triggered (DET) techniques are most liked choice for the researchers in the field of digital VLSI design because of its high-performance and low-power consumption standard. Dual edge triggered techniques give the similar throughput at half of the clock frequency as compared to the single edge triggered (SET) techniques. Dual edge triggered techniques can reduce the 50% power consumption and increase the total system power savings. The low-power glitch-free novel dual edge triggered flip-flop (DET-FF) design is proposed in this paper. Still now, existing DET-FF designs are constructed by using either C-element circuit or 1P-2N structure or 2P-1N structure, but the proposed novel design is designed by using the combination of C-element circuit and 2P-1N structure. In this design, if any glitch affects one of the structures, then it is nullified by the other structure. To control the input loading, the two circuits are merged to share the transistors connected to the input. In the proposed design, we have used an internal dual feedback structure. The proposed design reduces the delay and power consumption and increases the speed and efficiency of the system.

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Section: Resultsmentioning

confidence: 99%

Section: Existing Designsmentioning

confidence: 99%

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A Glitch-Free Novel DET-FF in 22 nm CMOS for Low-Power Application

Singar

Joshi

Ghosh

2018

Journal of Nanotechnology

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“…Meanwhile, two-phase clocked DET-FFs utilize complementary clock signals (CLK, CLKB) for reliable operation [22,23,24,25,26,27]. Since they do not rely on pulses, they are more robust against PVT variation than pulse-based FFs, and, thanks to symmetric structure, the layout can be made compact despite the use of many transistors.…”

Section: Introductionmentioning

confidence: 99%

A PVT variation-tolerant static single-phase clocked dual-edge triggered flip-flop for aggressive voltage scaling

Lee

2019

IEICE Electron. Express

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A novel static single-phase clocked (SSPC) dual-edge triggered flip-flop (DET-FF) is proposed to allow energy-efficient operation with aggressive voltage scaling. By employing two static latches with a singlephase clock, contention and clock phase mismatch is avoided, which significantly improves tolerance to PVT variations. The post-layout simulation performed with 28 nm CMOS technology shows that the proposed SSPC DET-FF consumes less power and has significantly better powerperformance trade off (PDP) than prior-art DET-FFs. Our Monte Carlo analysis also showed that its supply voltage can be aggressively scaled down to 0.3 V even with PVT variations.

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“…Power dissipation of these flip-flops is less dependent on input signal transitions in between the clock edges at the cost of increased power dissipation due to clock activity. [7] implementations [1] This paper presents novel static DET flip-flop designs that use C-elements. The paper consists of five sections.…”

mentioning

confidence: 99%