International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318)
DOI: 10.1109/iedm.1999.824290
|View full text |Cite
|
Sign up to set email alerts
|

New LV-BPD (low voltage buried photo-diode) for CMOS imager

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
2

Citation Types

0
2
0

Publication Types

Select...
5
2

Relationship

1
6

Authors

Journals

citations
Cited by 15 publications
(2 citation statements)
references
References 0 publications
0
2
0
Order By: Relevance
“…However, when considering the necessary factors such as the higher fill factor, high-speed readout, on-chip ADC and signal processing functions, higher spatial resolution, and the overall functionalities and the chip-size versus the cost factor, the selection of the CMOS image sensor technology seems to be more advantageous [6][7][8][9][10].…”
Section: Introductionmentioning
confidence: 98%
“…However, when considering the necessary factors such as the higher fill factor, high-speed readout, on-chip ADC and signal processing functions, higher spatial resolution, and the overall functionalities and the chip-size versus the cost factor, the selection of the CMOS image sensor technology seems to be more advantageous [6][7][8][9][10].…”
Section: Introductionmentioning
confidence: 98%
“…They have significant advantages compared with three-transistor (3-Tr) CMOS image sensors. Firstly, the 4-Tr scheme can use pinned photodiodes (PPDs) [ 2 , 3 , 4 , 5 , 6 ] to reduce the dark current. Secondly, the complete charge transfer by the PPD [ 2 ] realizes “first reset, later signal” and correlated double sampling (CDS) [ 7 ], which eliminates both the reset noise at the floating diffusion node and the low frequency noise at the source follower amplifier.…”
Section: Introductionmentioning
confidence: 99%