New Memory Load Optimization Approach for Software Implementation of Irregular LDPC Encoder/Decoder

Benhayoun, Mhammed; Razi, Mouhcine; Mansouri, Anas; Ahaitouf, Ali

doi:10.1109/wits.2019.8723841

Cited by 3 publications

(2 citation statements)

References 9 publications

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“…The efficient memory parity check matrix optimization proposed in [22,23] is used to reduce the memory requirement. It is clear that the error correcting performance of the proposed algorithm is better than the others.…”

Section: Performance Evaluationmentioning

confidence: 99%

Low-Complexity LDPC Decoding Algorithm Based on Layered Vicinal Variable Node Scheduling

Benhayoun

Razi

Mansouri

et al. 2022

Modelling and Simulation in Engineering

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The informed dynamic scheduling (IDS) strategies for the low-density parity check (LDPC) decoding have shown superior performance in error correction and convergence speed, particularly those based on reliability measures and residual belief propagation (RBP). However, the search for the most unreliable variable nodes and the residual precomputation required for each iteration of the IDS-LDPC increases the complexity of the decoding process which becomes more sequential, making it hard to exploit the parallelism of signal processing algorithms available in multicore platforms. To overcome this problem, a new, low-complexity scheduling system, called layered vicinal variable nodes scheduling (LWNS) is presented in this paper. With this LWNS, each variable node is updated by exchanging intrinsic information with all its associated control and variable nodes before moving to the next variable node updating. The proposed scheduling strategy is fixed by a preprocessing step of the parity control matrix instead of calculation of the residuals values and by computation of the most influential variable node instead the most unreliable metric. It also allows the parallel processing of independent Tanner graph subbranches identified and grouped in layers. Our simulation results show that the LWNS BP have an attractive convergence rate and better error correction performance with low complexity when compared to previous IDS decoders under the white Gaussian noise channel (AWGN).

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Section: Performance Evaluationmentioning

confidence: 99%

Low-Complexity LDPC Decoding Algorithm Based on Layered Vicinal Variable Node Scheduling

Benhayoun

Razi

Mansouri

et al. 2022

Modelling and Simulation in Engineering

Self Cite

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show abstract

“…For applications that require a large codes length, to speed up the decoding process and optimize memory, we adopt the same method as we reported previously [31], we have stored just the positions of the 1s in the H matrix. This method simplifies the check for the 1s during decoding and decreases the time processing by reducing the number of memory access.…”

Section: Hardware Implementationmentioning

confidence: 99%

An improvement and a fast DSP implementation of the bit flipping algorithms for low density parity check decoder

Razi

Benhayoun

Mansouri

et al. 2021

IJECE

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<span lang="EN-US">For low density parity check (LDPC) decoding, hard-decision algorithms are sometimes more suitable than the soft-decision ones. Particularly in the high throughput and high speed applications. However, there exists a considerable gap in performances between these two classes of algorithms in favor of soft-decision algorithms. In order to reduce this gap, in this work we introduce two new improved versions of the hard-decision algorithms, the adaptative gradient descent bit-flipping (AGDBF) and adaptative reliability ratio weighted GDBF (ARRWGDBF). An adaptative weighting and correction factor is introduced in each case to improve the performances of the two algorithms allowing an important gain of bit error rate. As a second contribution of this work a real time implementation of the proposed solutions on a digital signal processors (DSP) is performed in order to optimize and improve the performance of these new approchs. The results of numerical simulations and DSP implementation reveal a faster convergence with a low processing time and a reduction in consumed memory resources when compared to soft-decision algorithms. For the irregular LDPC code, our approachs achieves gains of 0.25 and 0.15 dB respectively for the AGDBF and ARRWGDBF algorithms.</span>

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Efficient Memory Parity Check Matrix Optimization for Low Latency Quasi Cyclic LDPC Decoder

Benhayoun¹,

Razi²,

Mansouri³

et al. 2020

Lecture Notes in Electrical Engineering

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New Memory Load Optimization Approach for Software Implementation of Irregular LDPC Encoder/Decoder

Cited by 3 publications

References 9 publications

Low-Complexity LDPC Decoding Algorithm Based on Layered Vicinal Variable Node Scheduling

Low-Complexity LDPC Decoding Algorithm Based on Layered Vicinal Variable Node Scheduling

An improvement and a fast DSP implementation of the bit flipping algorithms for low density parity check decoder

Efficient Memory Parity Check Matrix Optimization for Low Latency Quasi Cyclic LDPC Decoder

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