New observations on complex RTN in scaled high-&amp;#x03BA;/metal-gate MOSFETs &amp;#x2014; The role of defect coupling under DC/AC condition

Ren, Pengpeng; Peng, Hao; Liu, Changze; Wang, Runsheng; Jiang, Xiaobo; Qiu, Yingxin; Huang, Ru; Guo, Shaofeng; Luo, Mulong; Zou, Jibin; Li, Meng; Wang, Jianping; Wu, Jingang; Liu, Jinhua; Bu, Weihai; Wong, Waisum; Yu, Scott; Wu, Hanming; Lee, Shiuh-Wuu; Wang, Yangyuan

doi:10.1109/iedm.2013.6724731

Cited by 19 publications

(8 citation statements)

References 4 publications

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“…The number of traps present is proportional to device area and the single trap impact is inversely proportional to it 44,45 . It is also often observed that RTN is not always consistent where some traps may only be active when a dominating trap is in a certain state 46 . This can result in Id measurements like or similar to Fig.…”

Section: Resultsmentioning

confidence: 99%

“…The maximum Vg is 1.2 V. The Vd can be adjusted between 0.1 V and 0.5 V to achieve the optimal result. The effect of Vg and Vd on RTN traps has also been studied previously 46,51 . Typically, an increase in Vg will decrease the capture time and increase the emission time with a given Vd and the exact relationship being highly device dependant.…”

Section: Discussionmentioning

confidence: 99%

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Random-telegraph-noise-enabled true random number generator for hardware security

Brown

Zhang

Zhou

et al. 2020

Sci Rep

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The future security of Internet of Things is a key concern in the cyber-security field. One of the key issues is the ability to generate random numbers with strict power and area constrains. “True Random Number Generators” have been presented as a potential solution to this problem but improvements in output bit rate, power consumption, and design complexity must be made. In this work we present a novel and experimentally verified “True Random Number Generator” that uses exclusively conventional CMOS technology as well as offering key improvements over previous designs in complexity, output bitrate, and power consumption. It uses the inherent randomness of telegraph noise in the channel current of a single CMOS transistor as an entropy source. For the first time multi-level and abnormal telegraph noise can be utilised, which greatly reduces device selectivity and offers much greater bitrates. The design is verified using a breadboard and FPGA proof of concept circuit and passes all 15 of the NIST randomness tests without any need for post-processing of the generated bitstream. The design also shows resilience against machine learning attacks performed by the LSTM neural network.

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Section: Resultsmentioning

confidence: 99%

Section: Discussionmentioning

confidence: 99%

Random-telegraph-noise-enabled true random number generator for hardware security

Brown

Zhang

Zhou

et al. 2020

Sci Rep

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“…To explain the obtained results in which the appearance probability and amplitude of RTN were changed statistically by the drain current conditions, we consider the channel percolation model. [24][25][26][27][28][29] Owing to the effects of random discrete dopants in the channel and other random fluctuations of device parameters, the Si surface potential fluctuates. This results in forming one or several channel percolation paths that dominate the current flow from source to drain.…”

Section: Resultsmentioning

confidence: 99%

“…26) From the atomistic technology computer aided design (TCAD) simulation, it is reported that the number of percolation paths increases as the gate overdrive voltage increases, i.e., the drain current increases. 29) Figure 10 shows a schematic illustration of the impacts of drain current on the appearance probability and amplitude of RTN. Here, we consider the two cases in each range of the Gumbel plot under the large (20 µA) and small (0.1 µA) drain current conditions shown in Fig.…”

Section: Resultsmentioning

confidence: 99%

“…From the obtained results, we discuss the effects of drain current on the probability and amplitude of RTN using the channel percolation model. [24][25][26][27][28][29] with pinned photodiode technology. It consists of horizontal and vertical shift registers, a pixel array including measured SF transistors, current sources, and output buffers.…”

Section: Introductionmentioning

confidence: 99%

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Effect of drain current on appearance probability and amplitude of random telegraph noise in low-noise CMOS image sensors

Ichino

Mawaki

Teramoto

et al. 2018

Jpn. J. Appl. Phys.

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Random telegraph noise (RTN), which occurs in in-pixel source follower (SF) transistors, has become one of the most critical problems in highsensitivity CMOS image sensors (CIS) because it is a limiting factor of dark random noise. In this paper, the behaviors of RTN toward changes in SF drain current conditions were analyzed using a low-noise array test circuit measurement system with a floor noise of 35 µV rms . In addition to statistical analysis by measuring a large number of transistors (18048 transistors), we also analyzed the behaviors of RTN parameters such as amplitude and time constants in the individual transistors. It is demonstrated that the appearance probability of RTN becomes small under a small drain current condition, although large-amplitude RTN tends to appear in a very small number of cells.

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Low-Frequency Noise in III–V, Ge, and 2D Transistors

et al. 2020

Noise in Nanoscale Semiconductor Devices

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New observations on complex RTN in scaled high-κ/metal-gate MOSFETs — The role of defect coupling under DC/AC condition

Cited by 19 publications

References 4 publications

Random-telegraph-noise-enabled true random number generator for hardware security

Random-telegraph-noise-enabled true random number generator for hardware security

Effect of drain current on appearance probability and amplitude of random telegraph noise in low-noise CMOS image sensors

Low-Frequency Noise in III–V, Ge, and 2D Transistors

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