New Three Dimensional High Density S-SGT Flash Memory Architecture using Self-Aligned Interconnection Fabricating Technology without Photo Lithography Process for Tera Bits and Beyond

Abstract

New three dimensional S-SGT flash memory architecture can achieve the cell area of 3.88F 2 per bit using 0.2um design rule. The new architecture is realized by stacking two select transistors and two memory cells in vertically on each pillar located in a two-dimensional array matrix. Each gate and each interconnection of this new architecture are fabricated by vertical self-aligned process and horizontal self-aligned process simultaneously using conformal deposited HTO and RIE without using photo lithography process. The new three dimensional S-SGT flash memory architecture is applicable to high-density nonvolatile memories as large as Tera-bits and beyond.