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New three dimensional S-SGT flash memory architecture can achieve the cell area of 3.88F 2 per bit using 0.2um design rule. The new architecture is realized by stacking two select transistors and two memory cells in vertically on each pillar located in a two-dimensional array matrix. Each gate and each interconnection of this new architecture are fabricated by vertical self-aligned process and horizontal self-aligned process simultaneously using conformal deposited HTO and RIE without using photo lithography process. The new three dimensional S-SGT flash memory architecture is applicable to high-density nonvolatile memories as large as Tera-bits and beyond.

5-q37, FACS IMILE: (Q7 436) 5-277 4 l.Introduction Recently high density flash memory has been expected to replace the external mass storage device market d computers. For this application, fast random access, low power consumption, and small erase unit size are required.

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