Niagara: A 32-Way Multithreaded Sparc Processor

Kongetira, Poonacha; Aingaran, K.; Olukotun, Kunle

doi:10.1109/mm.2005.35

Cited by 786 publications

(502 citation statements)

References 5 publications

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“…The mechanism for dynamically scaling the number of workers is already in place to support fault recovery. In systems with multithreaded cores (e.g., UltraSparc T1 [16]), we spawn one worker per hardware thread. This typically maximizes the system throughput even if an individual task takes longer.…”

Section: Concurrency and Locality Managementmentioning

confidence: 99%

Evaluating MapReduce for Multi-core and Multiprocessor Systems

Ranger

Raghuraman

Penmetsa

et al. 2007

2007 IEEE 13th International Symposium on High Performance Computer Architecture

769

447

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This paper evaluates the suitability of the MapReduce model for multi-core and multi-processor systems. MapReduce was created by Google for application development on data-centers with thousands of servers. It allows programmers to write functional-style code that is automatically parallelized and scheduled in a distributed system.We describe Phoenix, an implementation of MapReduce for shared-memory systems that includes a programming API and an efficient runtime system. The Phoenix runtime automatically manages thread creation, dynamic task scheduling, data partitioning, and fault tolerance across processor nodes. We study Phoenix with multi-core and symmetric multiprocessor systems and evaluate its performance potential and error recovery features. We also compare MapReduce code to code written in lower-level APIs such as P-threads. Overall, we establish that, given a careful implementation, MapReduce is a promising model for scalable performance on shared-memory systems with simple parallel code.

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Section: Concurrency and Locality Managementmentioning

confidence: 99%

Evaluating MapReduce for Multi-core and Multiprocessor Systems

Ranger

Raghuraman

Penmetsa

et al. 2007

2007 IEEE 13th International Symposium on High Performance Computer Architecture

769

447

View full text Add to dashboard Cite

show abstract

“…Due to the ability of masking the cache miss latency with dynamically scheduling instructions, deep out-of-order pipelines have a higher tolerance to L1 cache misses than shallow in-order pipelines Therefore, performance effects of cache affinity could vary depending on the pipeline architecture. In our study we consider processors with both deep super-scalar out-of-order pipelines (Clovertown) [10] and shallow in-order single-issue pipelines (Niagara) [7].…”

Section: Methodsmentioning

confidence: 99%

Performance Implications of Cache Affinity on Multicore Processors

Kazempour

Fedorova

Alagheband

2008

Lecture Notes in Computer Science

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Abstract. Cache affinity between a process and a processor is observed when the processor cache has accumulated some amount of the process state, i.e., data or instructions. Cache affinity is exploited by OS schedulers: they tend to reschedule processes to run on a recently used processor. On conventional (unicore) multiprocessor systems, exploitation of cache affinity improves performance. It is not yet known, however, whether similar performance improvements would be observed on multicore processors. Understanding these effects is crucial for design of efficient multicore scheduling algorithms. Our study analyzes performance effects of cache affinity exploitation on multicore processors. We find that performance improvements on multicore uniprocessors are not significant. At the same time, performance improvements on multicore multiprocessors are rather pronounced.

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“…There is still considerable debate regarding the highlevel organization of CMPs [14][15][16]. Therefore, we use two different CMP architectures that are similar to current general-purpose, high-performance CMP implementations for our interference investigations.…”

Section: A Chip Multiprocessor Architecturesmentioning

confidence: 99%

A Quantitative Study of Memory System Interference in Chip Multiprocessor Architectures

Jahre

Grannæs

Natvig

2009

2009 11th IEEE International Conference on High Performance Computing and Communications

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Abstract-The potential for destructive interference between running processes is increased as Chip Multiprocessors (CMPs) share more on-chip resources. We believe that understanding the nature of memory system interference is vital to achieve good fairness/complexity/performance trade-offs in CMPs. Our goal in this work is to quantify the latency penalties due to interference in all hardware-controlled, shared units (i.e. the onchip interconnect, shared cache and memory bus). To achieve this, we simulate a wide variety of realistic CMP architectures. In particular, we vary the number of cores, interconnect topology, shared cache size and off-chip memory bandwidth. We observe that interference in the off-chip memory bus accounts for between 63% and 87% of the total interference impact while the impact of cache capacity interference can be lower than indicated by previous studies (between 5% and 32% of the total impact). In addition, as much as 11% of the total impact can be due to uncontrolled allocation of shared cache Miss Status Holding Registers (MSHRs).

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Niagara: A 32-Way Multithreaded Sparc Processor

Cited by 786 publications

References 5 publications

Evaluating MapReduce for Multi-core and Multiprocessor Systems

Evaluating MapReduce for Multi-core and Multiprocessor Systems

Performance Implications of Cache Affinity on Multicore Processors

A Quantitative Study of Memory System Interference in Chip Multiprocessor Architectures

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