Nickel Silicide and Nickel Germanosilicide Processing in a Near-Isothermal Cavity: Sheet Resistance Curves for Blanket Ni/Si and Ni/SiGe Substrates and Electrical Data for CMOS Devices

Abstract

NiSi has become the preferred material in CMOS technology for source and drain contacts and is being considered as a metal gate material as well. With strain engineering demanding different types of strain for NMOS and PMOS transistors, Ni metal reacts with substrates that have a wide variety of properties (i.e. chemical composition, doping level, different crystalline phases). All of the relevant material combinations need to be taken into account when designing and optimizing an IC manufacturing process. The first part of this study was performed on 300 mm diameter blanket wafers and focuses on Ni metal reactions with lightly doped single-crystal Si and Si0.8Ge0.2. The former is typically used for sources and drains for NMOS transistors (need tensile stress in the channel for electron mobility enhancement), the latter for PMOS transistors (need compressive stress in the channel for hole mobility enhancement). The phase transformation curves for Ni/Si and Ni/Si0.8Ge0.2 are used for identifying the IC process window. In the second part of this study, we used 300 mm diameter device wafers (K8 microprocessor, 65 nm design rule) and targeted four distinct annealing conditions that were chosen based on the blanket wafer experiments.

Thermal Silicidation of Ni/SiGe and Characterization of Resulting Nickel Germanosilicides

“…Thermal silicidation was performed using TiN/Ni/Si 1-x Ge x /Si/SiO 2 /Si wafers with different Ge content in a stacked hotplate-based SAO-302LP system designed for 300 mm wafers. 9,[21][22][23][24] Thicknesses of the TiN, Ni, Si 1-x Ge x , Si and SiO 2 layers were 5, 9, 80, 20 and 140 nm, respectively. Physical vapor deposited (PVD or sputtered) TiN (5 nm) capped Ni films (9 nm) were used.…”

“…Details of the annealing system (SAO-302LP), wafer temperature profile and other low temperature process applications (NiSi, Cu annealing and SOG annealing) results have been reported elsewhere. 9,[21][22][23][24] Unlike other annealing systems, the SAO-302LP system does not control wafer temperature directly and annealing time is also counted differently. For easy understanding, wafer temperature profiles at hot plate temperature set points of 200 °C, 300 °C and 400 °C are plotted in Fig.…”

“…[5][6][7][8] Formation and stability of thin metal germanosilicides have been studied for many popular metals, such as; Ti, Co, Ni, Cu, Pd and Pt. [9][10][11] For further device performance enhancement, by designing fully depleted MOSFETs, device fabrication on Si 1-x Ge x /Si/SiO 2 /Si has been actively investigated for more than a decade. Detailed study and proper understanding of metal germanosilicide formation on Si 1-x Ge x /Si/SiO 2 /Si are necessary to properly integrate the system in device designs and fabrication.…”

“…Previously, we have reported preliminary results on nickel germanosilicide formation and characterization of resulting silicides. 9,20 In the study, formation and characterization of nickel germanosilicide has been studied using TiN-capped Ni/Si 1-x Ge x /Si/SiO 2 /Si wafers with different Ge content in nearly isothermal annealing environments. As a continuing effort, we report the thermal silicidation characteristics of additional Ni/Si 1-x Ge x wafers with various Ge content under different annealing temperatures in the range of 225 °C ∼ 400 °C in N 2 ambient.…”

Formation and Characterization of Nickel Germanosilicide on Si1-xGex/Si/SiO2/Si

“…[5][6][7][8] Formation and stability of thin metal germanosilicides have been studied for many popular metals, such as; Ti, Co, Ni, Cu, Pd and Pt. [9][10][11] For further device performance enhancement by designing fully depleted MOSFETs, device fabrication on Si 1-x Ge x /Si/SiO 2 /Si has been actively investigated for more than a decade. Detailed study and proper understanding of metal germanosilicide formation on Si 1-x Ge x /Si/SiO 2 /Si are necessary to properly integrate the system in device design and fabrication.…”