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Formation of titanium silicide was studied using a "hot wall" single wafer rapid thermal furnace (SRTF) system. Average sheet resistance and unifonmity of TiSi2 films before and after processing, as well as process repeatability were evaluated. We also collected data for annealing of implanted wafers, oxide thickness & uniformity before and after dry and wet oxidation. We use this data to demonstrate process repeatability for anneals in the SRTF system. Comparison with wafers processed with Altis Semiconductor tool of record (TOR) gave some useful information regarding differences between wafers processed in lamp-based RTA and SRTF systems. INTRODUCTIONRapid thermal processing (RTP) is widely used in device manufacturing today [1][2][3][4], providing operational flexibility and single wafer tracing compared to large batch fumaces. Two types of RTP system (amp-based single-wafer processing RTP system and non-lamp-based RTP system) have been developed and introduced in the market. The "cold wall" lampbased RTP systems have very poor energy efficiency and require complicated temperature measurement/control algorithms; in addition, system hook-up and preventive maintenance time as well as spare parts & energy consumption are economic parameters which are signiftcant.The dual chamber, single wafer rapid thermal furnace (SRTF) with a vacuum loadlock is described. The SRTF system is vacuum-and atmospheric-pressure compatible. The "hot wall" process chamber has no moving parts and can be used in 100% oxygen as well as oxygenfree environments. Thermal characteristics and process performance of the system are investigated in detail in the temperature range of 200-1150'C. A very high ramp rate (A150°C/s) was obtained in the high temperature region (A1150°C) while the electric power consumption was kept minimal (<3.5kW per process chamber at 11 50°C). Typical throughput for 60s process in a dual chamber is chamber system is -60 wph.In this study, excellent process characterization results & performance of the SRTF system has been demonstrated in TiSi2 formation, with supporting data from dry and wet RTO and 11B+ inplanted 200 mm Si wafer RTP. EXPERIMENTALThe "hot wall" process chamber of the SRTF system used in this study is shown in Figure 1. It is made of a tube of clear quartz and has three quartz standoffs; it is resistively heated to the desired process temperature which is then kept constant. The process tube uses no moving parts 1-4244-0648-X/06/$20.00 32006 IEEE -255 -for design simplicity and system reliability. The wafer is placed on the quartz standoffs (8-9 mm tall) in the middle of the quartz process tube. The separation between the wafer and the quartz walls is kept at AOmm for both upward and downward directions. The quartz process tube is located in a SiC cavity which acts as a heat distributor to create an isothermal process environment. The SiC cavity is surrounded by a three-zone heater assembly. The temperature of the SiC cavity is monitored and controled at a predetermined process temperature by three em...

NiSi has become the preferred material in CMOS technology for source and drain contacts and is being considered as a metal gate material as well. With strain engineering demanding different types of strain for NMOS and PMOS transistors, Ni metal reacts with substrates that have a wide variety of properties (i.e. chemical composition, doping level, different crystalline phases). All of the relevant material combinations need to be taken into account when designing and optimizing an IC manufacturing process. The first part of this study was performed on 300 mm diameter blanket wafers and focuses on Ni metal reactions with lightly doped single-crystal Si and Si0.8Ge0.2. The former is typically used for sources and drains for NMOS transistors (need tensile stress in the channel for electron mobility enhancement), the latter for PMOS transistors (need compressive stress in the channel for hole mobility enhancement). The phase transformation curves for Ni/Si and Ni/Si0.8Ge0.2 are used for identifying the IC process window. In the second part of this study, we used 300 mm diameter device wafers (K8 microprocessor, 65 nm design rule) and targeted four distinct annealing conditions that were chosen based on the blanket wafer experiments.

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