NISHA: A fault-tolerant NoC router enabling deadlock-free Interconnection of Subnets in Hierarchical Architectures

Neishaburi, M.H.; Žilić, Željko

doi:10.1016/j.sysarc.2012.12.002

Cited by 11 publications

(4 citation statements)

References 34 publications

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“…A transient and permanent fault tolerant based Enhanced Reliability Aware Virtual Channel Architecture (ERAVC), presented by [33] and more comprehensive version [34] utilizes the virtual channels in such a way that input channel being idle because faulty neighboring routers utilize it efficiently to improve the performance. Authors in [35] proposed a Partial Virtual Channel (PVC) sharing router.…”

Section: Related Workmentioning

confidence: 99%

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Protector: A Permanent Fault Resilient Router Architecture for Network on Chip

Baloch

Hussain

Baig

2020

Mehran Univ. res. j. eng. technol.

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The decreasing size of the transistor has increased the vulnerability towards faults. Increasing number of cores on a single chip has made the concept of Network on Chip (NoC) a standard communication backbone among cores. This facility comes with vulnerability of faults in the system due to decreasing size of transistors. A permanent fault in the network leads to undesirable consequence such as permanent blocking of flits or failure of the whole router. Preserving the router in the operational state has a significant impact on the reliability of the system. Permanent fault in buffers and pipeline stages of the router has a high impact on performance. The proposed router architecture Protector provides faults protection to both buffers and pipelines stages by exploiting the concepts of borrowing from other resources, using bypass paths and by creating multiple paths to reach output. The proposed router incurred an area overhead of 30% as compared to the baseline design. Reliability analysis using Silicon Protection Factor indicates that the proposed router has better fault tolerance efficiency as compared to state of the art. Latency analysis using PARSEC and SPLASH-2 benchmarks indicates proposed router incurs 13% and 16% latency overhead in the presence of faults.

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Section: Related Workmentioning

confidence: 99%

“…The significant portion of the router consists of buffers. They consume the most substantial fraction of the dynamic and static power [34] than the packet transmission [35]. It is evident that the probability of a permanent faults occurring in the input port is high because it occupies a larger area.…”

Section: Protector: Input Portmentioning

confidence: 99%

Protector: A Permanent Fault Resilient Router Architecture for Network on Chip

Baloch

Hussain

Baig

2020

Mehran Univ. res. j. eng. technol.

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“…A hierarchical table-based routing approach that considers faults for NoCs organized in subnetworks is presented in [14]. The focus of [14] is to maintain deadlock freedom of global routing after routing reconfiguration in subnetworks.…”

Section: Routing Reconfigurationmentioning

confidence: 99%

“…The focus of [14] is to maintain deadlock freedom of global routing after routing reconfiguration in subnetworks. To provide deadlock freedom for each subnetwork one virtual channel (VC) is implemented which is used for communication with other subnetworks.…”

Section: Routing Reconfigurationmentioning

confidence: 99%

Fault Tolerant Routing for Hierarchically Organized Networks-on-Chip

Schley

Radetzki

2015

2015 23rd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing

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With increasing number of processing elements on a single chip, the size of the Network-on-Chip connecting the processing elements increases accordingly. This leads to new challenges for components such as fault diagnosis and routing because they do not scale with the size of the Network-on-Chip, e.g. regarding the required communication overhead or their implementation costs. A measure to avoid these scaling problems is to organize future Networks-on-Chip hierarchically.This paper presents a fault tolerant routing for Networks-on-Chip organized into hierarchical units where each unit manages its own routing. In case of link faults or failure of switches, the proposed approach enables the online adaptation of routing locally within each unit while deadlock freedom is globally ensured in the network. Experimental results of our approach for a 16x16 network show a speedup of three for routing reconfiguration compared to state-of-the-art approach. At the same time our approach achieves a memory reduction for routing tables by a factor of seven compared to flat network tables.

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System on chip failure rate assessment using the executable model of a system

Neishaburi

Žilić

2013

Computing

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NISHA: A fault-tolerant NoC router enabling deadlock-free Interconnection of Subnets in Hierarchical Architectures

Cited by 11 publications

References 34 publications

Protector: A Permanent Fault Resilient Router Architecture for Network on Chip

Protector: A Permanent Fault Resilient Router Architecture for Network on Chip

Fault Tolerant Routing for Hierarchically Organized Networks-on-Chip

System on chip failure rate assessment using the executable model of a system

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