To address the increasing demand for reliability in on-chip networks, we proposed a novel Reliability Aware Virtual channel (RAVC) NoC router micro-architecture that enables both dynamic virtual channel allocations and the rational sharing among the buffers of different input channels. In particular, in the case of failure in routers, the virtual channels of routers surrounding the faulty routers can be totally recaptured and reassigned to other input ports. Moreover, our proposed RAVC router isolates the faulty router from occupying network bandwidth. Experimental result shows that proposed micro-architecture provides 7.1% and 3.1 % average latency decrease under uniform and transpose traffic pattern. Considering the existence of failures in routers of on-chip network, RAVC provides 28% and 16% decrease in the average packet latency under the uniform and transpose traffic pattern respectively.

Today, real-time applications with critical constraints are usually run in an environment with Real-Time Operating System (RTOS). Services provided by RTOSs are severely exposed to faults which affect both functional and timing of the tasks running on the RTOS based system. In this paper, we introduce a new architecture for RTOS provides more robust services in term of Soft Errors (SEs). We evaluate and analyze robustness of the services due to SEs in two architectures, i.e. SW-RTOS and HW/SW-RTOS. Experimental results show more robust services were provided by HW/SW-RTOS versus purely SW-RTOS regarding SEs.

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With a significant increase in the complexity of cores and their intercommunications, there is a need to review and enhance traditional debug methods for System on Chips (SoCs). As new SoCs tend to have many cores, the interactions among cores through functional interconnects such as bus or Network on Chips (NoCs) are becoming so complex. Therefore, debug techniques should address not only validation of the computational part of a design but such techniques have to monitor and validate the communication and synchronization among cores inside SoCs. In this paper, we consider NoC as a functional interconnection among cores and propose debug aware network interface (NI) which is compatible with AXI standard. The proposed interface enables provides a mechanism for cross-trigger debugging. Transactions issued by a processing element connected to the proposed debug aware NI are monitored by the proposed cross-trigger unit and trace data and trigger events will be extracted and routed to another processing element or Shared Debugging Unit (SDU). SDU combines debug traces from different processing elements. The major benefits of using our proposed architectures for debugging over traditional techniques are as follows: 1) the proposed debug aware NI can detect, mark and bypass severe faulty conditions such as deadlocks resulting from design errors or electrical faults in real time 2) there is no need for a large internal trace memory inside processing element because SDU can communicate to the external memory 3) debugging of applications which are running on multiple processors can facilitate by means of available features inside the proposed trigger mechanism.

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