Reliability aware NoC router architecture using input channel buffer sharing

Abstract

To address the increasing demand for reliability in on-chip networks, we proposed a novel Reliability Aware Virtual channel (RAVC) NoC router micro-architecture that enables both dynamic virtual channel allocations and the rational sharing among the buffers of different input channels. In particular, in the case of failure in routers, the virtual channels of routers surrounding the faulty routers can be totally recaptured and reassigned to other input ports. Moreover, our proposed RAVC router isolates the faulty router from occupying network bandwidth. Experimental result shows that proposed micro-architecture provides 7.1% and 3.1 % average latency decrease under uniform and transpose traffic pattern. Considering the existence of failures in routers of on-chip network, RAVC provides 28% and 16% decrease in the average packet latency under the uniform and transpose traffic pattern respectively.

An infrastructure for debug using clusters of assertion-checkers

“…Moreover, Network on Chips (NoCs) routers should also be aware of the importance of design errors and faults [32][33][34], making the incorporation of debug infrastructures inside such routers an instrumental technique [29,30].…”

Debug Aware AXI-based Network Interface

“…TR keeps track of all the in-order transactions. The master shows its intention for having several in-order requests (transactions) by assigning the same transaction ID to them [20]. LUD must ensure that such transactions which may complete out of order are issued in order to the master.…”

“…To meet a critical time-to-market deadline, SoC designers usually resort to pre-designed Intellectual Property (IP) cores such as (processors, memories, DSPs, and other embedded cores). To carry out their demanding tasks embedded cores inside an SoC typically are interconnected through functional interconnects such as on-chip buses and Network-on-Chips (NoCs) [3] [7], [20], [21]. Although such a complex system must go through various verification steps to be ensured that embedded cores inside the system are compatible and the whole system is error-free, bugs still slip to the first silicon in a significant percentage.…”

A Novel Topology-Independent Router Architecture to Enhance Reliability and Performance of Networks-on-Chip

“…A single fault tolerance method is not an optimal solution for all types of faults [11]. Neishabouri et al [16] propose Reliability Aware Virtual Channel (RAVC) architecture for NoC. RAVC enables both dynamic VC allocation and reliability aware sharing among input channels.…”

“…Due to this, reliability of the manufactured devices is becoming endangered [17] [11]. There are a number of fault tolerant solutions available to deal with reliability at different abstraction levels for example routing algorithms [13] [25], architectures [16] [23] and error control coding schemes [7] [20]. Some of the fault tolerant NoC architectures proposed by researchers use intelligent routing algorithms [6] [5].…”