An infrastructure for debug using clusters of assertion-checkers

Neishaburi, M.H.; Žilić, Željko

doi:10.1016/j.microrel.2012.04.016

Cited by 6 publications

(3 citation statements)

References 24 publications

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“…A variety of on-chip instrumentation techniques have been introduced to observe efficiently and non-intrusively the intermediate signals of different components in a complex system [1], [3], [10], [16], [24], [25], [37].…”

Section: Related Workmentioning

confidence: 99%

“…The authors in [21] and [37] investigated a method for clustering assertion checkers inside the design; however, they have not integrated these clusters of checkers inside a trigger unit. Assertion checkers are considered as a building block in our proposed trigger generation tool.…”

Section: Related Workmentioning

confidence: 99%

“…System designers are able to define both expected and prohibited behaviors of a design using a wide range of Boolean expressions combined with extended regular expressions and a large set of temporal operators. Verification languages such as PSL (Property Specification Language, IEEE 1850 standard) [37] and SVA (System Verilog Assertions) are standardized for ABV [38].…”

Section: Assertion Languagesmentioning

confidence: 99%

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On a New Mechanism of Trigger Generation for Post-Silicon Debugging

Neishaburi

Žilić

2014

IEEE Trans. Comput.

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The main goal of post-silicon debugging is to locate errors undetected during the pre-silicon verification. Although high speed of hardware prototype can be leveraged to expedite running a large number of realistic test vectors, the low level of observability and controllability of signals inside a prototype is a big concern. Design for Debug (DFD) techniques aim to improve the observability of signals and speed up the root-cause analysis of errors. Incorporation of an Embedded Logic Analyzer (ELA) is introduced as one of the practical DFD techniques. An ELA contains a trigger unit that controls conditions for which trace signals should be captured in a buffer for post-processing. In this paper, we propose a tool to generate hierarchical triggers, providing compact trace information for root-cause analysis. Major advantages of our technique as a means to generate trigger units are: 1) failure localization and root-cause analysis is expedited by keeping the hierarchical trace of interactions leading to failures, 2) overlapped failure patterns can be found by mechanism which results in a 60-65% reduction in hardware overhead compared to the previously proposed method, 3) it can be parameterized to generate several units, making it possible to incorporate checkers into scarce silicon area and enabling on-chip debugging by means of time-multiplexing scheme.

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