NoC-MRAM architecture for memory-based computing: Database-search case study

Rizk, Mostafa; Diguet, Jean Philippe; Onizawa, Naoya; Baghdadi, Amer; Sepulveda, M-J.; Akgul, Yeter; Gripon, Vincent; Hanyu, Takahiro

doi:10.1109/newcas.2017.8010167

Cited by 4 publications

(2 citation statements)

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“…The flags corresponding to these clusters is set to "0". Also, the addresses of the processing modules (P [2], P [3], P [4], P [7], and P [8]) are specified in the second part of each segment. The choice of the PE is made dynamically with a fairness load-balancing policy.…”

Section: B Noc Implementationmentioning

confidence: 99%

“…Finally, the effectiveness of the proposed approach is demonstrated through a relevant case study of a database search application implemented with neuromorphic architecture based on Sparse-Neural-Network (SNN) [1]. This paper presents five new contributions that improve significantly the performances compared to our previous work [2]: i) an original type of power-gated MRAM memory called Type III. It is based on an asymmetric read/write scheme and allows for significant power reductions with respect to previous solutions; ii) rather than a single manager, multiple manager modules can be working concurrently; iii) the processing elements are not statically but dynamically allocated; iv) processing elements are implemented as dedicated hardware components and they are included in the global power budget; v) design and synthesis of all modules, including MRAM devices, are done using 65nm technology node.…”

Section: Introductionmentioning

confidence: 99%

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Networked Power-Gated MRAMs for Memory-Based Computing

Diguet

Onizawa

Rizk

et al. 2018

IEEE Trans. VLSI Syst.

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Emerging non-volatile memory technologies open new perspectives for original computing architectures. In this paper, we propose a new type of flexible and energy-efficient architecture that relies on power-gated distributed Magnetoresistive Random-Access Memory (MRAM). The proposed architecture uses a Network-on-Chip (NoC) to interconnect MRAM-based clusters, processing elements, and managers. The NoC distributes application-specific commands to MRAM devices by means of packets. Configurable Network Interfaces (NI) allow to transform MRAM devices into smart units able to respond to incoming commands. In this context, three types of MRAM designs are proposed with different power-gating policies and granularities. A relevant database search engine case study is considered to illustrate the benefits of this proposed architecture. It is implemented with a Sparse-Neural-Network (SNN) approach and simulated in SystemC with different scenarios including hundreds of database queries. Hardware designs and accurate power estimations have been conducted. The obtained results demonstrate important power reduction with database hit rates of about 94%. Targeting 65nm technology, energy savings reach 87% when compared with an SRAM-based implementation. Moreover, a new asymmetric read/write MRAM type provides from 39% to 50% energy reduction with respect to the other fixed-granularity models. This results in a low-power, highly scalable and configurable implementation of memory-based computing.

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