Noise and impedance of the SIROF utah electrode array

Sharma, Mohit; Gardner, A. Tye; Silver, Jason; Walker, Ross M.

doi:10.1109/icsens.2016.7808826

Cited by 5 publications

(3 citation statements)

References 11 publications

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“…The equivalent noise power spectral density (PSD) was estimated (Figure 10A,B) according to the real part of the impedance using Eq. (4) (Sharma et al, 2017). For both, bright Pt and Pt-black electrodes, the PSD shows 1/ f noise characteristics at low frequencies and reaches a plateau of thermal noise level (dominated by R s -noise as expected) at higher frequencies.…”

Section: Resultsmentioning

confidence: 99%

Optimal Electrode Size for Multi-Scale Extracellular-Potential Recording From Neuronal Assemblies

et al. 2019

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Advances in microfabrication technology have enabled the production of devices containing arrays of thousands of closely spaced recording electrodes, which afford subcellular resolution of electrical signals in neurons and neuronal networks. Rationalizing the electrode size and configuration in such arrays demands consideration of application-specific requirements and inherent features of the electrodes. Tradeoffs among size, spatial density, sensitivity, noise, attenuation, and other factors are inevitable. Although recording extracellular signals from neurons with planar metal electrodes is fairly well established, the effects of the electrode characteristics on the quality and utility of recorded signals, especially for small, densely packed electrodes, have yet to be fully characterized. Here, we present a combined experimental and computational approach to elucidating how electrode size, and size-dependent parameters, such as impedance, baseline noise, and transmission characteristics, influence recorded neuronal signals. Using arrays containing platinum electrodes of different sizes, we experimentally evaluated the electrode performance in the recording of local field potentials (LFPs) and extracellular action potentials (EAPs) from the following cell preparations: acute brain slices, dissociated cell cultures, and organotypic slice cultures. Moreover, we simulated the potential spatial decay of point-current sources to investigate signal averaging using known signal sources. We demonstrated that the noise and signal attenuation depend more on the electrode impedance than on electrode size, per se , especially for electrodes <10 μm in width or diameter to achieve high-spatial-resolution readout. By minimizing electrode impedance of small electrodes (<10 μm) via surface modification, we could maximize the signal-to-noise ratio to electrically visualize the propagation of axonal EAPs and to isolate single-unit spikes. Due to the large amplitude of LFP signals, recording quality was high and nearly independent of electrode size. These findings should be of value in configuring in vitro and in vivo microelectrode arrays for extracellular recordings with high spatial resolution in various applications.

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Section: Resultsmentioning

confidence: 99%

Optimal Electrode Size for Multi-Scale Extracellular-Potential Recording From Neuronal Assemblies

et al. 2019

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“…Recently, we performed wideband spectral measurements of implanted electrodes [ 37 , 38 , 39 , 40 ] ( Figure 3 ). These measurements characterize the noise at high frequency as thermal in origin, on the basis of impedance magnitude and phase measurements.…”

Section: Rapidly Multiplexed Neural Recording: Theory and Practicamentioning

confidence: 99%

Acquisition of Neural Action Potentials Using Rapid Multiplexing Directly at the Electrodes

et al. 2018

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Neural recording systems that interface with implanted microelectrodes are used extensively in experimental neuroscience and neural engineering research. Interface electronics that are needed to amplify, filter, and digitize signals from multichannel electrode arrays are a critical bottleneck to scaling such systems. This paper presents the design and testing of an electronic architecture for intracortical neural recording that drastically reduces the size per channel by rapidly multiplexing many electrodes to a single circuit. The architecture utilizes mixed-signal feedback to cancel electrode offsets, windowed integration sampling to reduce aliased high-frequency noise, and a successive approximation analog-to-digital converter with small capacitance and asynchronous control. Results are presented from a 180 nm CMOS integrated circuit prototype verified using in vivo experiments with a tungsten microwire array implanted in rodent cortex. The integrated circuit prototype achieves <0.004 mm2 area per channel, 7 µW power dissipation per channel, 5.6 µVrms input referred noise, 50 dB common mode rejection ratio, and generates 9-bit samples at 30 kHz per channel by multiplexing at 600 kHz. General considerations are discussed for rapid time domain multiplexing of high-impedance microelectrodes. Overall, this work describes a promising path forward for scaling neural recording systems to numbers of electrodes that are orders of magnitude larger.

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“…Furthermore, intracortical spikes and SNN models are already intrinsically compatible, no further processing is required to transform a continuous signal into a spiking one, as happens when other forms of neural activity are used in place of action potentials. This work presents a spike-based neural decoding system implemented on FPGA that exploits the computational efficiency of SNNs to decode the displacement of a handle moved during a delayed reach-to-grasp task [13], recorded using a 96-channel multi-electrode array (MEA) [14]. Moreover, the neural signal is pre-processed in real-time to extract the MUA by using a multiplier-less spike detector, mapped in the Programmable Logic (PL).…”

Section: Introductionmentioning

confidence: 99%

On-FPGA Spiking Neural Networks for End-to-End Neural Decoding

2023

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In the last decades, deep learning neural decoding algorithms have gained momentum in the field of neural interfaces and neural processing systems. However, to be deployed on low-budget portable devices while maintaining real-time operability, these models must withstand strict computational and power limitations. This work presents a spike decoding system implemented on a low-end Zynq-7010 FPGA, which includes a multiplier-less spike detection pipeline and a spiking-neural-network-based decoder mapped in the programmable logic. We tested the system on two publicly available datasets and achieved comparable results with state-of-the-art neural decoders that use more complex deep learning models. The system required 7.36 times fewer parameters than the smallest architecture tested on the same dataset. Moreover, by exploiting the spike sparsity property of the neural signal, the total amount of computations is reduced by about 90% during a test carried out on real recorded data. The low computational complexity of the chosen spike detection setup, combined with the power efficiency of spiking neural networks, makes this prototype a well-suited choice for low-power real-time neural decoding at the edge.INDEX TERMS Neural decoding, spike detection, spiking neural network, FPGA, real-time, low-power.

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Noise and impedance of the SIROF utah electrode array

Cited by 5 publications

References 11 publications

Optimal Electrode Size for Multi-Scale Extracellular-Potential Recording From Neuronal Assemblies

Optimal Electrode Size for Multi-Scale Extracellular-Potential Recording From Neuronal Assemblies

Acquisition of Neural Action Potentials Using Rapid Multiplexing Directly at the Electrodes

On-FPGA Spiking Neural Networks for End-to-End Neural Decoding

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