Non-binary LDPC code with multiple memory reads for multi-level-cell (MLC) flash

Aslam, Chaudhry Adnan; Guan, Yong Liang; Cai, Kui

doi:10.1109/apsipa.2014.7041532

Cited by 13 publications

(5 citation statements)

References 26 publications

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“…However, this multipleread operation causes significant throughput degradation. Meanwhile, the authors in [6]- [8] proposed the application of NB-LDPC codes for MLC NAND flash memory, and the soft-reliability-based QSPA was employed for decoding. The QSPA, however, suffered a significant throughput degradation owing to high decoding complexity.…”

Section: Introductionmentioning

confidence: 99%

Iterative Pseudo-Soft-Reliability-Based Majority-Logic Decoding for NAND Flash Memory

Park

Chung

2021

IEEE Access

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This paper proposes a decoding algorithm for nonbinary low-density parity-check (NB-LDPC) codes, aiming to improve the error rate performance for NAND flash memory. Several NB-LDPC decoding methods for NAND flash memory have been studied. Some approaches rely on hard decisions, and these are relatively simple but do not have a good error rate performance. Others are based on soft decisions that require multiple reads for each flash memory cell, leading to significant memory throughput degradation. To improve the error rate performance without suffering performance degradation owing to multiple reads, an iterative pseudo-soft-reliability-based decoding algorithm is proposed. Using Galois field addition to calculate the Hamming distance at the initialization, the proposed algorithm not only improves the error rate performance but also reduces the average number of iterations compared with those of conventional hard-decision-based decoding algorithms. INDEX TERMSError correction codes, Hamming distance, Hard decision, Iterative hard-reliability-based majority-logic decoding algorithm, NAND flash memory, Nonbinary low-density parity-check codes

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Section: Introductionmentioning

confidence: 99%

Iterative Pseudo-Soft-Reliability-Based Majority-Logic Decoding for NAND Flash Memory

Park

Chung

2021

IEEE Access

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“…[1,[3][4][5][6][7] The research results illustrate that both the channel dopant fluctuation and the trap generation in the tunnel oxide layer aggravate the RTN impact on the cell's threshold voltage control. [8][9][10][11][12][13][14][15][16][17][18][19] On the other hand, RTN is a conspicuous issue for multi-level flash memory due to the stringent requirement of V th distribution since multi-level cell program levels are closer to each other. Small RTN fluctuations could confuse the adjacent levels and lead to the errors of read operation.…”

Section: Introductionmentioning

confidence: 99%

Random telegraph noise on the threshold voltage of multi-level flash memory

Liao

et al. 2017

Chinese Phys. B

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We investigate the impact of random telegraph noise (RTN) on the threshold voltage of multi-level NOR flash memory. It is found that the threshold voltage variation (∆V th ) and the distribution due to RTN increase with the programmed level (V th ) of flash cells. The gate voltage dependence of RTN amplitude and the variability of RTN time constants suggest that the large RTN amplitude and distribution at the high program level is attributed to the charge trapping in the tunneling oxide layer induced by the high programming voltages. A three-dimensional TCAD simulation based on a percolation path model further reveals the contribution of those trapped charges to the threshold voltage variation and distribution in flash memory.

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“…As a consequence, flash data reliability is degraded [1]- [3]. To overcome the reliability issues, strong error correcting codes (ECCs), such as low-density parity-check (LDPC) codes, are seriously considered [4], [5]. To reap full benefits of LDPC code, it is desirable to have LDPC decoder's input values quantized as finely as possible.…”

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confidence: 99%

Read and Write Voltage Signal Optimization for Multi-Level-Cell (MLC) NAND Flash Memory

Aslam

Guan

Cai

2016

IEEE Trans. Commun.

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The multi-level-cell (MLC) NAND flash channel exhibits non-stationary behavior over increasing program and erase (PE) cycles and data retention time. In this paper, an optimization scheme for adjusting the read (quantized) and write (verify) voltage levels to adapt to the non-stationary flash channel is presented. Using a model-based approach to represent the flash channel, incorporating the programming noise, random telegraph noise (RTN), data retention noise and cell-to-cell interference as major signal degradation components, the writevoltage levels are optimized by minimizing the channel error probability. Moreover, for selecting the quantization levels for the read-voltage to facilitate soft LDPC decoding, an entropybased function is introduced by which the voltage erasure regions (error dominating regions) are controlled to produce the lowest bit/frame error probability. The proposed write and read voltage optimization schemes not only minimize the error probability throughout the operational lifetime of flash memory, but also improve the decoding convergence speed. Finally, to minimize the number of read-voltage quantization levels while ensuring LDPC decoder convergence, the extrinsic information transfer (EXIT) analysis is performed over the MLC flash channel.

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Non-binary LDPC code with multiple memory reads for multi-level-cell (MLC) flash

Cited by 13 publications

References 26 publications

Iterative Pseudo-Soft-Reliability-Based Majority-Logic Decoding for NAND Flash Memory

Iterative Pseudo-Soft-Reliability-Based Majority-Logic Decoding for NAND Flash Memory

Random telegraph noise on the threshold voltage of multi-level flash memory

Read and Write Voltage Signal Optimization for Multi-Level-Cell (MLC) NAND Flash Memory

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