Read and Write Voltage Signal Optimization for Multi-Level-Cell (MLC) NAND Flash Memory

Abstract

The multi-level-cell (MLC) NAND flash channel exhibits non-stationary behavior over increasing program and erase (PE) cycles and data retention time. In this paper, an optimization scheme for adjusting the read (quantized) and write (verify) voltage levels to adapt to the non-stationary flash channel is presented. Using a model-based approach to represent the flash channel, incorporating the programming noise, random telegraph noise (RTN), data retention noise and cell-to-cell interference as major signal degradation components, the writevoltage levels are optimized by minimizing the channel error probability. Moreover, for selecting the quantization levels for the read-voltage to facilitate soft LDPC decoding, an entropybased function is introduced by which the voltage erasure regions (error dominating regions) are controlled to produce the lowest bit/frame error probability. The proposed write and read voltage optimization schemes not only minimize the error probability throughout the operational lifetime of flash memory, but also improve the decoding convergence speed. Finally, to minimize the number of read-voltage quantization levels while ensuring LDPC decoder convergence, the extrinsic information transfer (EXIT) analysis is performed over the MLC flash channel.

A Combinatorial Methodology for Optimizing Non-Binary Graph-Based Codes: Theoretical Analysis and Applications in Data Storage

“…Code 3 is an NB-PB-LDPC code defined over GF (4), with block length = 8480 bits, rate ≈ 0.90, and γ = 4. Code 4 is the result of optimizing Code 3 by attempting to remove the dominant GASTs (4, 4, 4, 6, 0), (6,4,4,10,0), (6,5,5,8,1), and (8, 4, 2, 15, 0) using the WCM framework (see [5]). Code 5 is the result of optimizing Code 4 for the asymmetric NLM channel by attempting to remove the OSTs in Table IV using It is demonstrated by Fig.…”

“…In the simulations of this subsection, Code 9 is an NB-PB-LDPC code defined over GF (4), with block length = 3996 bits, rate ≈ 0.89, and γ = 3. Code 10 is the result of optimizing Code 9 for the asymmetric NLM channel (with 6 reads this time) by attempting to remove the dominant GASTs (4, 2, 2, 5, 0), (4, 3, 2, 5, 0), (5, 2, 2, 5, 1), (6, 0, 0, 9, 0), (6, 1, 0, 9, 0), (6, 1, 1, 7, 1), (6,2,2,5,2), and (6, 2, 2, 8, 0) using the WCM framework.…”

“…We also reuse Code 6 in this subsection (its parameters are stated in the previous subsection). Code 13 is the result of optimizing Code 6 for the asymmetric CHMM channel (with 6 reads) by attempting to remove the dominant GASTs (4, 4, 4, 6, 0), (6,4,4,11,0), and (7, 4, 3, 11, 1) in addition to the dominant OSTs (6, 5, 2, 11, 0), (7, 5, 3, 11, 1), (7,5,4,9,2), (7,6,6,8,2), (8,6,2,15,0), and (10,7,5,11,4) using the WCM framework.…”

“…20, upper panel, and its circulant power arrangement is given in Fig. 20, lower panel (see also [55] and [58] (6,6,6,9,0), and (8, 2, 2, 15, 0) using the WCM framework. Fig.…”

Deep Learning-Aided Dynamic Read Thresholds Design for Multi-Level-Cell Flash Memories

“…In the literature, several techniques have been proposed to design the read thresholds [6][7][8][9][10]. For example, a "constantratio" (CR) non-uniform quantization method was proposed by observing that more errors occur in the overlapped areas of adjacent distribution functions [6].…”