Non-PR Sn-3.5Ag Bumping on a Fast Filled Cu-Plug by PPR Current

Hong, Sung Chul; Jung, Do Hyun; Lee, Wang Gu; Kim, Won-Joong; Jung, Jae Pil

doi:10.1109/tcpmt.2013.2240765

Cited by 4 publications

(8 citation statements)

References 35 publications

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“…Using a precise ratio of C 4 F 8 and SF 6 makes it possible to form the vertical shape of TSV. In the vertical shape, current waveform control can avoid void or seam defects [9,30] or additives into plating solution [31]. However, an unsuitable plating solution and plating condition can cause high current density at the entrance of TSV, which closes the opening and causes voids and seams inside the TSV.…”

Section: Through-si-via 21 Tsv Formation and Drie Technologymentioning

confidence: 99%

“…However, Cu is easy to be oxidized and it can be consumed during Cu electroplating by dissolution into electroplating solution. There is a report of using the Au layer to prevent oxidization and to achieve higher chemical stability [9,36,37]. Hong et al [9] has coated SiO 2 , Ti, and Au as protection and seed layers inside the TSV.…”

Section: Tsv Inner Wall Coatingmentioning

confidence: 99%

“…There is a report of using the Au layer to prevent oxidization and to achieve higher chemical stability [9,36,37]. Hong et al [9] has coated SiO 2 , Ti, and Au as protection and seed layers inside the TSV.…”

Section: Tsv Inner Wall Coatingmentioning

confidence: 99%

“…Bumping without the lithography method has advantages such as omitting the following steps: PR (photoresist) coating, film masking, UV (ultraviolet) exposure, patterning, and PR stripping processes [76,80]. The author also uses the non-PR process in various studies [9,78,79]. The standard equilibrium potential of Ag is more positive than that of Sn.…”

Section: Solder Bump By Electroplatingmentioning

confidence: 99%

“…The process of TSV technology consists of the following steps: (a) forming a fine through-hole in a silicon wafer, (b) coating a functional thin layer on the inner wall of the through-hole, (c) filling the through-hole with a conductive material, and (d) exposing the through-hole and making a thin wafer through polishing (CMP, chemical mechanical polishing), bumping, and lamination processes. Since the TSV technology makes a direct connection path inside the chip, it is possible to minimize the length of the connection part when connecting to other chips [9][10][11]. This reduces electrical resistance and speeds up data transmission.…”

Section: Introductionmentioning

confidence: 99%

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A Review on the Fabrication and Reliability of Three-Dimensional Integration Technologies for Microelectronic Packaging: Through-Si-via and Solder Bumping Process

Cho

Seo

Kim

et al. 2021

Metals

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With the continuous miniaturization of electronic devices and the upcoming new technologies such as Artificial Intelligence (AI), Internet of Things (IoT), fifth-generation cellular networks (5G), etc., the electronics industry is achieving high-speed, high-performance, and high-density electronic packaging. Three-dimensional (3D) Si-chip stacking using through-Si-via (TSV) and solder bumping processes are the key interconnection technologies that satisfy the former requirements and receive the most attention from the electronic industries. This review mainly includes two directions to get a precise understanding, such as the TSV filling and solder bumping, and explores their reliability aspects. TSV filling addresses the DRIE (deep reactive ion etching) process, including the coating of functional layers on the TSV wall such as an insulating layer, adhesion layer, and seed layer, and TSV filling with molten solder. Solder bumping processes such as electroplating, solder ball bumping, paste printing, and solder injection on a Cu pillar are discussed. In the reliability part for TSV and solder bumping, the fabrication defects, internal stresses, intermetallic compounds, and shear strength are reviewed. These studies aimed to achieve a robust 3D integration technology effectively for future high-density electronics packaging.

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Section: Through-si-via 21 Tsv Formation and Drie Technologymentioning

confidence: 99%

Section: Tsv Inner Wall Coatingmentioning

confidence: 99%

Section: Tsv Inner Wall Coatingmentioning

confidence: 99%

Section: Solder Bump By Electroplatingmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

A Review on the Fabrication and Reliability of Three-Dimensional Integration Technologies for Microelectronic Packaging: Through-Si-via and Solder Bumping Process

Cho

Seo

Kim

et al. 2021

Metals

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Through-Silicon via Submount for Flip-Chip LEDs

Chang

Chen

et al. 2017

ECS J. Solid State Sci. Technol.

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A blue light emitting diode (LED) was prepared by a flip-chip (FC) LED and three-dimensional through-silicon via (3D-TSV) technique. The experimental results indicated that the diameter and length of the Si via were about 180 μm and 400 μm, respectively. The Cu was uniformly and high density filled in each TSV, and the average resistance was about 0.14 m . It was also found that the 96.43Sn-3.57at%Ag bumps were electroplated on the Cu plugged TSVs of a silicon substrate, and these were smoother at 250 • C. After reflow, a 3D blue light emitting diode was prepared by peak bonding at 250 The increasing use of light emitting diodes (LED) in products has promoted the development of higher power, greater density, and lower cost devices. Compared with conventional LED, flip-chip (FC) LED 1-3 have a number of advantages, such as about twice the light output of conventional LED. Flip-chip technology not only shortens the production process, but also significantly reduces thermal resistance and results in a greater heat dissipation rate than seen with the traditional gold wire bonded LED. Moreover, the direct contact of the electrodes or bumps with the package structure can substantially enhance the cooling effect. The flip-chip approach can also remove wire bonding and other wire frame processes, and so these LED can be used with high current drivers.4,5 Therefore, FC LED are attracting growing interest due to their greater heat dissipation, better light emission, higher reliability, and more efficient bonding processes than seen with traditional wire bonded LED.The typical bonding process recommended by chip companies for FC LED is Au/Sn eutectic bonding.6 However, eutectic Sn-Ag alloy is a promising candidate among the various Pb-free solder materials for use with FC LED, and the resulting Sn-Ag alloy bumps 7 can be easily obtained by annealing the Ag/Sn metal stack.There is also demand for new packaging processes for FC LED. 8The use of three-dimensional (3D) packaging through-silicon via (TSV) technology allows a high density of vertical interconnects, unlike 2D packing, as shown in Figure 1. 3D TSV ICs have the following advantages: (1) reduced connection lengths, and thus smaller parasitic capacitance, inductance, and resistance; (2) high-speed low-power interconnects; and (3) a combination of monolithic and multifunctional integration. In this study, a blue LED was prepared using an FC LED and the 3D-TSV technique. We thus propose a new method to achieve 3D LED packing. The detailed fabrication of the TSV and the electrooptical properties of the fabricated are also discussed. ExperimentalFigure 2 presents a schematic diagram of the fabrication process for the 3D LED. A P-type 400 μm thick Si wafer was used as the bottom substrate. Photolithography was used to make a mask for etching the Al layer. A positive type photoresist, AZ-1500, was spin-coated to a thickness of 2 μm with a rotation speed of 500 rpm for 15 s, followed by 3000 rpm for 30 s. The Al layer was etched by wet etching, after using acetone to remove...

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Advanced 3D Through-Si-Via and Solder Bumping Technology: A Review

Jang,

Sharma,

Jung

2023

Materials

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Three-dimensional (3D) packaging using through-Si-via (TSV) is a key technique for achieving high-density integration, high-speed connectivity, and for downsizing of electronic devices. This paper describes recent developments in TSV fabrication and bonding methods in advanced 3D electronic packaging. In particular, the authors have overviewed the recent progress in the fabrication of TSV, various etching and functional layers, and conductive filling of TSVs, as well as bonding materials such as low-temperature nano-modified solders, transient liquid phase (TLP) bonding, Cu pillars, composite hybrids, and bump-free bonding, as well as the role of emerging high entropy alloy (HEA) solders in 3D microelectronic packaging. This paper serves as a guideline enumerating the current developments in 3D packaging that allow Si semiconductors to deliver improved performance and power efficiency.

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Non-PR Sn-3.5Ag Bumping on a Fast Filled Cu-Plug by PPR Current

Cited by 4 publications

References 35 publications

A Review on the Fabrication and Reliability of Three-Dimensional Integration Technologies for Microelectronic Packaging: Through-Si-via and Solder Bumping Process

A Review on the Fabrication and Reliability of Three-Dimensional Integration Technologies for Microelectronic Packaging: Through-Si-via and Solder Bumping Process

Through-Silicon via Submount for Flip-Chip LEDs

Advanced 3D Through-Si-Via and Solder Bumping Technology: A Review

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