Nonlinear behavioural model of charge pump PLLs

Abstract

Despite the nonlinear nature of even the simplest versions of phase locked loops (PLLs), linear models are still used during the first phases of the design of modern PLLs. Even though the linear model may represent a crude approach, its use is justified by the fact that accurate numerical simulations often require a too large amount of CPU time, being PLLs by construction stiff circuits, characterised by very different time scales. This aspect has triggered the need for compact models that allow fast and accurate numerical simulations. The scientific literature numbers several models that have been developed with different approaches and tailored to different simulation environments. In this context, we propose a nonlinear model of a type-II PLL, which (1) considers both the switching behaviour of the phase/frequency detector and charge pump and the complex dynamics (including the presence of amplitude and phase noise) of the voltage controlled oscillator, (2) is compact and can be easily implemented in modern mixed analog/digital simulators as a behavioural block, and (3) allows the simulation of spurs owing to the nonlinearities of both the charge pump and the fractional frequency divider

Amplitude and phase dynamics of noisy oscillators

“…By converse, multiplying (9) to the left by Z T yields Because and R are Itô processes, they satisfy relations of type d = dt + dW t and dR = dt + dW t , respectively. By Itô lemma (d ) 2 = 2 T dt, d dR = 2 T dt.…”

Design of a 1‐GSample/s 9‐b double sampling track‐and‐hold amplifier in BiCMOS technology

“…Higher operation temperature of the BJT device leads to lower g m of bipolar device and thus the SNDR of the DTHA being degraded [42]. The mismatch between ideally equal, symmetrical devices represents a significant cause of performance degradation for analog circuits [43][44][45][46][47][48]. In the case of Figure 3, the mismatch between the upper sampling path (from the node V OP _ MA1 to the node V OP ) and the lower sampling path (from the node V OP _ MA2 to the node V OP ) impacts the dynamic performance of the proposed DTHA.…”

Dynamic behavioral modeling of nonlinear circuits using a novel recurrent neural network technique

“…There are several techniques for modeling nonlinear circuits: equivalent circuits, 13 model order reduction, [14][15][16] behavioral modeling, 17,18 statistical modeling approaches, 19 etc. [20][21][22][23] In equivalent circuit-based approaches, the device is converted to an equivalent circuit which has simpler circuit topology.…”