2016
DOI: 10.1109/mm.2016.35
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Nonvolatile Processor Architectures: Efficient, Reliable Progress with Unstable Power

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Cited by 38 publications
(20 citation statements)
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“…Sanyam et al in their recent research [93] on wear bench application showed that high performance can be achieved for deep learning along with other wearable applications (e.g., image compression, audio play back and video rendering) using Out of Order 32 bit CPU core with SIMD feature (e.g., ARM-A15 with NEON). Non-volatile processor architecture has been proposed [94] for energy harvesting IoT device to maximize the forward progress of IoT application in unstable and intermittent power supply environment. This paper considers out-of-order core as a base line processor for IoT wearable applications and introduces memristive accelerator to offload compute intensive CNN calculations from the core not only to reduce core dynamic power consumption but also to limit data movement between memory and core.…”
Section: Mobile Iot Applicationsmentioning
confidence: 99%
“…Sanyam et al in their recent research [93] on wear bench application showed that high performance can be achieved for deep learning along with other wearable applications (e.g., image compression, audio play back and video rendering) using Out of Order 32 bit CPU core with SIMD feature (e.g., ARM-A15 with NEON). Non-volatile processor architecture has been proposed [94] for energy harvesting IoT device to maximize the forward progress of IoT application in unstable and intermittent power supply environment. This paper considers out-of-order core as a base line processor for IoT wearable applications and introduces memristive accelerator to offload compute intensive CNN calculations from the core not only to reduce core dynamic power consumption but also to limit data movement between memory and core.…”
Section: Mobile Iot Applicationsmentioning
confidence: 99%
“…Broadly, these can be classified into two categories; software-based approaches [28,29], where the system's state (e.g. core and general-purpose registers, and main RAM memory) is saved into a Non-Volatile Memory (NVM) before a power failure occurs and restored once the power supply recovers, and hardware-assisted approaches [30,31], where the entire system is designed to be non-volatile (e.g. a unified low-power NVM system with non-volatile core and general-purpose registers).…”
Section: Transient Computing Techniquesmentioning
confidence: 99%
“…Architectural approaches (sometimes referred to as NonVolatile Processors, or NVPs) have also been proposed for transient computing, which provide hardware support for maintaining and saving state using NVM elements [10].…”
Section: B Transient Computingmentioning
confidence: 99%