Nonvolatile Spin-Based Radiation Hardened Retention Latch and Flip-Flop

Amirany, Abdolah; Marvi, Fahimeh; Jafari, Kian; Rajaei, Ramin

doi:10.1109/tnano.2019.2946108

Cited by 31 publications

(17 citation statements)

References 41 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…As shown in Fig. 2(b), the design proposed in [15] is mainly composed of two inverters, two parallel CEs (in the dotted rectangle), some signal-controlled transistors and a pair of complementary MTJs. The CEs provide the soft-error tolerance and the MTJs provide the NV feature.…”

Section: B Previous Workmentioning

confidence: 99%

“…However, the internal nodes of the design are direct inputs of the MTJ cells in the backup operation, resulting in large delay. To mitigate the drawbacks of the design in [15], the design proposed in [16] does not use peripheral circuits and additional control signals. However, this design cannot provide any DNU hardening.…”

Section: B Previous Workmentioning

confidence: 99%

“…By using seven 3-input CEs, the design in [19] can provide the DNU tolerance. However, it uses [15], (c) design in [16], (d) design in [18] and (e) design in [19].…”

Section: B Previous Workmentioning

confidence: 99%

See 2 more Smart Citations

A Radiation-Hardened Non-Volatile Magnetic Latch with High Reliability and Persistent Storage

Yan

Dingl

Zhou

et al. 2022

2022 IEEE 31st Asian Test Symposium (ATS)

View full text Add to dashboard Cite

With technology scaling down, the vulnerability of circuits to radiation and the increase of static power have become severe concerns. Spintronic devices such as magnetic tunnel junction (MTJ) have been developed to cope with many concerns, among which reliability concerns [1]. Spintronic devices have attractive properties, such as non-volatility and compatibility with conventional CMOS fabrication process. Based on an advanced triple-path dual-interlocked-storage-cell (TPDICE) and MTJs, this paper proposes a radiation-hardened non-volatile magnetic latch, namely M-TPDICE, that can completely tolerate single-node upsets (SNUs) and double-node upsets (DNUs). Simulations of the proposed latch with the HSPICE tool with a 45 nm CMOS technology model have demonstrated the effectiveness of the proposed latch.

show abstract

Section: B Previous Workmentioning

confidence: 99%

Section: B Previous Workmentioning

confidence: 99%

See 1 more Smart Citation

A Radiation-Hardened Non-Volatile Magnetic Latch with High Reliability and Persistent Storage

Yan

Dingl

Zhou

et al. 2022

2022 IEEE 31st Asian Test Symposium (ATS)

View full text Add to dashboard Cite

show abstract

“…If the width of the information to be protected is not the root of equation (2), then SEC-DED codes can also be shortened to fit the information size by using the same number of parity bits. In this case, equation (2) is now given by: (3) where k' is the unprotected information size, and l is the difference between k' and k that needs to be shortened and . protect caches, the number of memory cells that store the parity bits in the tag RAM is usually smaller than in the data RAM because tags are shorter than data.…”

Section: Extension For Stronger Codesmentioning

confidence: 99%

Protection of Associative Memories Using Combined Tag and Data Parity (CTDP)

Liu

Reviriego

Lombardi

2021

IEEE Trans. Nanotechnology

View full text Add to dashboard Cite

As emerging memories are utilized in processors as main memory, they must also coexist with CMOS memories; for instance SRAMs, are used to implement smaller, but faster associative memories. These hybrid designs exploit the advantages of both types of memories to achieve better performance. For some applications, the improvement in performance for on-chip associative memories is crucial for the overall computing system. For CMOS memories, soft errors are a major concern because they flip bits and can lead to data corruption and even a system failure. Error Detection and Correction Codes (EDCCs) are commonly used to protect memories against soft errors. In associative memories, an entry is formed by a tag and its associated data (or value). EDCCs are typically used to separately protect the tag and the data. This paper considers the protection of associative memories in which false negatives do not cause a failure. A Combined Tag and Data Parity (CTDP) protection scheme is proposed. This new approach utilizes a single parity bit per entry, so it reduces the number of parity bits needed to protect an entry as well as the memory size. The proposed scheme also reduces the complexity of read operations; it incurs the lowest circuit overhead for the protection circuitry in terms of area, delay and power consumption when compared to other schemes found in the technical literature. This makes the proposed scheme germane to associative memories used in hybrid designs that combine SRAMs and emerging memories. The extension of the proposed scheme to stronger codes is also discussed.

show abstract

“…Indeed, in this scenario, it could be easier for a Single Event Transient (SET) to induce, on the writing/reading transistors, a charge transfer that results in a bit flip. Trying to handle these challenges, radiationhardened peripheral circuit designs have been proposed in [16], [17] and [18]. The solution proposed in [18] has a radiation hardening capability below 100 fC while showing a negligible performance degradation and low area overhead.…”

Section: Introduction and Related Workmentioning

confidence: 99%

Spin-Transfer Torque Magnetic Tunnel Junction for Single-Event Effects Mitigation in IC Design

Coi

Pendina

Prenat

et al. 2020

IEEE Trans. Nucl. Sci.

View full text Add to dashboard Cite

For embedded systems in harsh environments, a radiation robust circuit design is still an open challenge. As complementary metal oxide semiconductor (CMOS) processes get denser and smaller, their immunity towards particle strikes decreases drastically. Due to its radiation effects good tolerance and its inherent non-volatility, Spin-Transfer Torque Magnetic Tunnel Junction (STT-MTJ) is considered a promising candidate for high reliability electronics. Nevertheless, when integrated in CMOS circuit, these magnetic devices could be still affected by upsets. To decrease the probability of this occurrence, a radiation robust setup is used to calibrate a physics-based 20 nm MTJ compact model, integrated in a 28 nm Fully Depleted Silicon on Insulator Technology. Thus, a radiation hardening by design (RHBD) solution is presented, where a non-volatile sequential block enables one to mitigate the Single Event Effects (SEEs).

show abstract

Nonvolatile Spin-Based Radiation Hardened Retention Latch and Flip-Flop

Cited by 31 publications

References 41 publications

A Radiation-Hardened Non-Volatile Magnetic Latch with High Reliability and Persistent Storage

A Radiation-Hardened Non-Volatile Magnetic Latch with High Reliability and Persistent Storage

Protection of Associative Memories Using Combined Tag and Data Parity (CTDP)

Spin-Transfer Torque Magnetic Tunnel Junction for Single-Event Effects Mitigation in IC Design

Contact Info

Product

Resources

About