NoRD: Node-Router Decoupling for Effective Power-gating of On-Chip Routers

Abstract

While power-gating is a promising technique to mitigate the increasing static power of a chip, a fundamental requirement is for the idle periods to be sufficiently long to compensate for the power-gating and performance overhead. On-chip routers are potentially good targets for power optimizations, but few works have explored effective ways of power-gating them due to the intrinsic dependence between the node and router -any packet (sent, received or forwarded) must wakeup the router before being transferred, thus breaking the potentially long idle period into fragmented intervals. Simulation shows that directly applying conventional power-gating techniques would cause frequent state-transitions and significant energy and performance overhead. In this paper, we propose NoRD (Node-Router Decoupling), a novel power-aware on-chip network approach that provides for power-gating bypass to decouple the node's ability for transferring packets from the powered-on/off status of the associated router, thereby maximizing the length of router idle periods. Full system evaluation using PARSEC benchmarks shows that the proposed approach can substantially reduce the number of state-transitions, completely hide wakeup latency from the critical path of packet transport and eliminate node-network disconnection problems. Compared to an optimized conventional power-gating technique applied to on-chip routers, NoRD can further reduce the router static energy by 29.9% and improve the average packet latency by 26.3%, with only 3% additional area overhead.

BlackOut: Enabling fine-grained power gating of buffers in Network-on-Chip routers

“…NoRD [5] improves previous power-gating methodologies by focusing on node-router decoupling. By bypassing the input/output ports, the network interface is directly connected to the network, thus communication is allowed even if the router is powered off.…”

Applying Partial Power-Gating to Direction-Sliced Network-on-Chip

“…A router parking method is proposed in [3] to power-gate routers when the connected core is idle, but it needs to flush private caches before turning off routers, which may cause serious performance decrease. The node-router disconnection referred to by [12] severely limits power-gating being effectively used in on-chip routers due to the limitation of break-even time, long wake-up delay. The problem is that a packet injected by an active core/sending-router may meet a sleeping receiving-router and has to suspend transfer and wait for the sleeping receiver being awakened due to the disconnection between the active sender and the sleeping receiver.…”

“…Originating the idea of guaranteeing full connectivity, these researches [12][13][14] provide a fully connected path to avoid the disconnection problem. The NoRD [12] introduces a bypass ring path to connect all nodes completely; then packets can be transmitted in the bypass ring to avoid long wake-up latency when meeting a sleeping router.…”

“…The NoRD [12] introduces a bypass ring path to connect all nodes completely; then packets can be transmitted in the bypass ring to avoid long wake-up latency when meeting a sleeping router. However, The packets' average latency brought by the bypass ring may inevitably increase proportionately with the square of network scale.…”

Deadline, Energy and Buffer-Aware Task Mapping Optimization in NoC-Based SoCs Using Genetic Algorithms

“…Its adoption improves the network throughput and allows the providing of QoS (Quality-of-Service). However, it impacts greatly on the area occupied by the NoC circuitry and may account for more than half of the static power dissipated by the routers [3].…”