NoSQ: Store-Load Communication without a Store Queue

Sha, Tingting; Martin, Milo M. K.; Roth, Aaron

doi:10.1109/mm.2007.17

Cited by 22 publications

(53 citation statements)

References 13 publications

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“…In the second case, store-load pairs that fit within the processor window can be speculatively identified, and the destination register of the load mapped to the source register of the store [3,4]. This is referred to as Speculative Memory Bypassing (SMB).…”

Section: Introductionmentioning

confidence: 99%

“…Although both optimizations have been extensively covered in previous work [1,3,5,6,7,4], studies that implement sharing through the PRF [1,3,6] generally failed to precisely describe how register sharing is actually handled. Most studies consider the adjunction of a reference counter to each physical register.…”

Section: Introductionmentioning

confidence: 99%

“…Instead of going through the Store Queue (SQ) and copying the data of a store to the destination register of a dependent load, it is much more efficient to rename the destination register of the load to the source register of the store, i.e., perform Speculative memory Bypassing (SMB) directly through the Physical Register File (PRF) [3]. An alternative is to use a dedicated buffer for SMB [5], which alleviates the need for register reference counting, but does not leverage the presence of the load data in the PRF.…”

Section: Introductionmentioning

confidence: 99%

“…Ultimately, we choose SMB as a way to evaluate our framework for physical register sharing, because is has been extensively studied in the literature [3,5,6,4]. Nonetheless, we still consider several improvements over existing SMB mechanisms.…”

Section: Introductionmentioning

confidence: 99%

“…First, we introduce the Instruction Distance predictor, in- spired from the Store Distance predictor of Sha et al [3]. This TAGE-like [9] predictor is accessed with the load PC and the global branch history, which are both available in the frontend.…”

Section: Introductionmentioning

confidence: 99%

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Cost effective physical register sharing

Seznec

2016

2016 IEEE International Symposium on High Performance Computer Architecture (HPCA)

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Sharing a physical register between several instructions is needed to implement several microarchitectural optimizations. However, register sharing requires modifications to the register reclaiming process: Committing a single instruction does not guarantee that the physical register allocated to the previous mapping of its architectural destination register is freeable anymore. Consequently, a form of register reference counting must be implemented.While such mechanisms (e.g., dependency matrix, per register counters) have been described in the literature, we argue that they either require too much storage, or that they lengthen branch misprediction recovery by requiring sequential rollback. As an alternative, we present the Inflight Shared Register Buffer (ISRB), a new structure for register reference counting. The ISRB has low storage overhead and lends itself to checkpoint-based recovery schemes, therefore allowing fast recovery on pipeline flushes.We illustrate our scheme with Move Elimination (shortcircuiting moves) and an implementation of Speculative Memory Bypassing (short-circuiting store-load pairs) that makes use of a TAGE-like predictor to identify memory dependencies. We show that the whole potential of these two mechanisms can be achieved with a small register tracking structure.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Cost effective physical register sharing

Seznec

2016

2016 IEEE International Symposium on High Performance Computer Architecture (HPCA)

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Flexible register management using reference counting

Battle

Hilton

Hempstead

et al. 2012

IEEE International Symposium on High-Performance Comp Architecture

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Conventional out-of-order processors that use a unified physical register file allocate and reclaim registers explicitly using a free list that operates as a circular queue. We describe and evaluate a more flexible register management scheme-reference counting. We implement reference counting using a bit-matrix with a column for every physical register and a row for every entity that can hold a physical register, e.g., an in-flight instruction. Columns are NOR'ed together to create a bitvector free list from which registers are allocated using priority encoders. We describe reference counting designs that support micro-architectural techniques including register file power gating, dynamic register move elimination, register file checkpointing, and latency tolerant execution. Performance and circuit simulation show that the energy cost of reference counting is low and is easily recouped by the savings of the techniques it enables.

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A position-insensitive finished store buffer

Gunadi

Lipasti

2007

2007 25th International Conference on Computer Design

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This paper presents the Finished Store Buffer (or FSB), an alternative and position-insensitive approach for building a scalable store buffer for an out-of-order processor. Exploiting the fact that only a small portion of in-flight stores are done executing (i.e. finished) and waiting for retirement, we are able to build a much smaller and more scalable store buffer. Our study shows that we only need at most half of the number of entries in a conventional store queue if we buffer only the stores that have finished execution. Entries in the store buffer are allocated at issue and disallocated on retirement. A clever encoder circuit is used to provide positional searches without an explicitly positional queue structure. While reducing the access latency and power consumption significantly, our technique has virtually no detrimental effect on per-cycle performance (IPC).

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NoSQ: Store-Load Communication without a Store Queue

Cited by 22 publications

References 13 publications

Cost effective physical register sharing

Cost effective physical register sharing

Flexible register management using reference counting

A position-insensitive finished store buffer

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