Not in Name Alone: A Memristive Memory Processing Unit for Real In-Memory Processing

Abstract

Data movement between processing and memory is the root cause of the limited performance and energy efficiency in modern von Neumann systems. To overcome the data-movement bottleneck, we present the memristive Memory Processing Unit (mMPU)-a real processing-in-memory system in which the computation is done directly in the memory cells, thus eliminating the necessity for data transfer. Furthermore, with its enormous inner parallelism, this system is ideal for data-intensive applications that are based on single instruction, multiple data (SIMD)-providing high throughput and energy-efficiency. Modern computers are typically based on the von Neumann architecture, in which the memory is separated from the processing space and programs are executed by moving data between the processing and memory units. This incessant data movement is the lead cause of the performance bottleneck known as the memory wall, which has increased in severity over the years as CPU speed improvements have surpassed those of memory speed and bandwidth. Furthermore, with the demise of Dennard scaling, energy-efficiency is becoming a major concern in modern computers; for example, moving data to an off-chip DRAM consumes four orders of magnitude more energy than the computation itself. 1 One approach to addressing the challenges arising from data movement is to move the computation closer to the memory. Both DRAM and emerging non-volatile memory technologies can provide ample intrinsic parallelism, which goes unutilized today due to pin-limited integrated circuit interfaces. Processing in memory (PIM) can leverage this intrinsic parallelism by avoiding the need for high-latency and high-energy chip-to-chip data transfers, thus yielding massively parallel, high-performance, energy-efficient processing systems.

In‐Memory Stateful Logic Computing Using Memristors: Gate, Calculation, and Application

“…As shown in the box of the green dotted line in Figure 10a, the stateful logic operation can be conducted simultaneously in different rows/columns when the data (gates) are aligned along the column/row. This characteristic corresponds to the framework of single instruction, multiple data, [30,110] in which a higher throughput can be obtained. For example, assuming that one multiplying unit exists in the ALU of a traditional CMOS-based single-core CPU, the read and write operation each takes 1024 cycles to conduct multiplication in 1024 pairs of 16-bit data.…”

“…The entire memristor-based stateful circuit is supported by the memristive memory processing unit (mMPU). [30,31] Figure 1g shows a simplified schematic of this mMPU. Shown in the same figure is the www.advancedsciencenews.com www.pss-rapid.com memory arithmetic logic unit (MALU), an in-memory computing block based on a memristive crossbar array, where the arithmetic calculation is executed through conducting and cascading the stateful logic operations.…”

Experimental Demonstration of Memristor-Aided Logic (MAGIC) Using Valence Change Memory (VCM)

“…Since NOR is functionally complete and MAGIC NOR can be easily mapped to a crossbar array, the MAGIC NOR gate was originally proposed as the basic building block for implementing in-memory logic in memristive memory processing units (mMPU) [27]. The initial execution step includes setting the output memristor to R ON .…”

Crossbar-Compatible Stateful Logic Using Phase Change Memory

“…Stateful logic enables PIM architectures such as the memristive memory processing unit (mMPU, Fig. 1b) 5 that offer massive intrinsic parallelism, high-performance, and energy-efficient processing, while maintaining backward compatibility with von Neumann architectures.…”