Experimental Demonstration of Memristor-Aided Logic (MAGIC) Using Valence Change Memory (VCM)

Hoffer, Barak; Rana, Vikas; Menzel, Stephan; Waser, Rainer; Kvatinsky, Shahar

doi:10.1109/ted.2020.3001247

Cited by 70 publications

(60 citation statements)

References 34 publications

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“…However, an alternative gate configuration of PMASM‐two‐3NOR involves the problem that the condition of | V SET | > 2 | V RESET | could hardly be met. [ 57 ] Therefore, an experimental demonstration of the PMASM‐two‐3NOR gate was barely made, as shown in Table 1.…”

Section: The Actual Implementation Of Stateful Logic Gatesmentioning

confidence: 99%

In‐Memory Stateful Logic Computing Using Memristors: Gate, Calculation, and Application

Park

Yoon

et al. 2021

Physica Rapid Research Ltrs

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Combining Boolean logic and nonvolatile memory functions, memristor-based stateful logic circuits can minimize data movement during the computing process to achieve futuristic in-memory computing. This may solve the problem of the von Neumann bottleneck in the current computing architecture. Herein, the recent developments in memristor-based stateful logic computation are discussed from several perspectives, including the device, circuit, operational principles, and applications. Stateful logic gates correspond to in-memory logic gates, with the inputs and outputs having identical physical entities, such as resistance. The developments in stateful logic primitive gates reported in the past decade are summarized. The influential factors in their actual implementation for stateful logic computation are also discussed. Then, methods for allocating the logic gates into the crossbar array are explained, which are for implementing the complex computing instances in the crossbar array. Finally, several data-intensive applications achieved using the in-memory computing method are discussed for the practical application of stateful logic in future computing systems.

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Section: The Actual Implementation Of Stateful Logic Gatesmentioning

confidence: 99%

In‐Memory Stateful Logic Computing Using Memristors: Gate, Calculation, and Application

Park

Yoon

et al. 2021

Physica Rapid Research Ltrs

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“…A smaller current appears despite the amplitudes of the SET (1.5 V) and RESET (−1.7 V) voltages are greater than the measured values with a read voltage of 0.2 V. In fact, we applied a transient triangle waveform pulse (20 ns) during the switching operation of the devices, and thus an unavoidable sampling signal collection offset and an RC delay may lead to a small current small than the actual peak current, which has also been observed in previous low current devices. [50] Based on the properties driven by the pulse voltage, we can realize the in-memory HD computations between A and B in the 1T1M memristor when using the aforementioned methodology. The four cases of "A = 0, B = 0," "A = 0, B = 1," "A = 1, B = 0" and "A = 1, B = 1" along with their corresponding test results are shown in Figures 4d-g, respectively.…”

Section: Hardware Realization and Performance Evaluation Of Hd Computations In 1t1m Memristorsmentioning

confidence: 99%

Implementation of Highly Reliable and Energy Efficient in‐Memory Hamming Distance Computations in 1 Kb 1‐Transistor‐1‐Memristor Arrays

Lin

Liu

et al. 2021

Adv Materials Technologies

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Highly efficient Hamming distance (HD) computations can significantly boost up modern data‐intensive algorithms. However, the traditional complementary metal–oxide–semiconductor devices configured circuits suffer from the huge power consumption with periphery complexity for HD computations. Herein, the implementation of highly reliable and energy efficient in‐memory HD computations in 1 Kb 1‐transistor‐1‐memristor (1T1M) TiN/HfOx/TaOx/TiN array chip is reported. 1T1M devices demonstrate a high on/off ratio of 50, high programming speed of 20 ns, and low energy consumption of 0.224 pJ bit−1. By modulating the 1T1M cell gate and source signal synergistically, the characteristic XOR operations of the binary information are executed in a reliable manner. Importantly, equipped with a stable low resistance state (LRS) distribution (coefficient of variation <11%), the developed 1T1M arrays can implement accurate HD computations between two 8‐bit strings and simultaneously store computing results in the memristors. The complementary studies demonstrate that the stable LRS is attributed to the TaOx built‐in compliance layer which facilitates the transistor surge current reduction during forming and SET, elaborating the significant potential for achieving reliable in‐memory HD computations. Such architecture manifests a 5‐ and 36.89‐fold enhancement of the processing latency and energy efficiency in comparison with latest reports, promoting the fan out of new in‐memory computing applications.

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“…Among LIM solutions [11][12][13][14][15][16][17], circuits based on resistive memory (RRAM) technology and the implication logic (IMPLY) offer ultra-dense back end of line (BEOL) integration. Currently, the main showstoppers [12,18] hindering the introduction of RRAM-based LIM circuits are the high energy per operation (as compared to CMOS gates), the degradation of the logic values of RRAMs during circuit operation, and the need to apply very precise voltage pulses (mV accuracy may be required [12,18,19]). Moreover, while in CMOS logic multiple operations can be computed in parallel on the same inputs, in IMPLY-based LIM circuits operations are carried out sequentially.…”

Section: Introductionmentioning

confidence: 99%

Multi-Input Logic-in-Memory for Ultra-Low Power Non-Von Neumann Computing

Zanotti¹,

Pavan²,

Puglisi³

2021

Micromachines

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Logic-in-memory (LIM) circuits based on the material implication logic (IMPLY) and resistive random access memory (RRAM) technologies are a candidate solution for the development of ultra-low power non-von Neumann computing architectures. Such architectures could enable the energy-efficient implementation of hardware accelerators for novel edge computing paradigms such as binarized neural networks (BNNs) which rely on the execution of logic operations. In this work, we present the multi-input IMPLY operation implemented on a recently developed smart IMPLY architecture, SIMPLY, which improves the circuit reliability, reduces energy consumption, and breaks the strict design trade-offs of conventional architectures. We show that the generalization of the typical logic schemes used in LIM circuits to multi-input operations strongly reduces the execution time of complex functions needed for BNNs inference tasks (e.g., the 1-bit Full Addition, XNOR, Popcount). The performance of four different RRAM technologies is compared using circuit simulations leveraging a physics-based RRAM compact model. The proposed solution approaches the performance of its CMOS equivalent while bypassing the von Neumann bottleneck, which gives a huge improvement in bit error rate (by a factor of at least 108) and energy-delay product (projected up to a factor of 1010).

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Experimental Demonstration of Memristor-Aided Logic (MAGIC) Using Valence Change Memory (VCM)

Cited by 70 publications

References 34 publications

In‐Memory Stateful Logic Computing Using Memristors: Gate, Calculation, and Application

In‐Memory Stateful Logic Computing Using Memristors: Gate, Calculation, and Application

Implementation of Highly Reliable and Energy Efficient in‐Memory Hamming Distance Computations in 1 Kb 1‐Transistor‐1‐Memristor Arrays

Multi-Input Logic-in-Memory for Ultra-Low Power Non-Von Neumann Computing

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