Novel application-specific signal processing architectures for wideband CDMA and TDMA applications

Subramanian, R.; Jha, Uma S.; Medlock, Jan; Woodthorpe, C.; Rieken, K.

doi:10.1109/vetecs.2000.851337

Cited by 14 publications

(4 citation statements)

References 9 publications

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“…Ideally one would want the power efficiency of a hardwired ASIC solution while maintaining the flexibility of a programmable processor, and the design space between the hardwired ASICs and the general-purpose DSP's attracts a significant amount of research interest [85,93,77,56,78,61,57,58,63,82,69,89,48,1,52,54]. A similar trend is identified in the SIA 2001 technology roadmap that predicts "flexibility-efficiency trade-off shifting away from general purpose processing" [12].…”

Section: Application/domain-specific Processorsmentioning

confidence: 92%

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Low-Power Digital Signal Processing

Oklobdzija¹

2001

The Computer Engineering Handbook

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This thesis introduces a novel approach to programmable and low power platform design for audio signal processing, in particular hearing aids. The proposed programmable platform is a heterogeneous multi-processor architecture consisting of small and simple instruction set processors called mini-cores as well as standard DSP/CPU-cores that communicate using message passing.The work has been based on a study of the algorithm suite covering the application domain. The observation of dominant tasks for certain algorithms (FIR, IIR, correlation, etc.) that require custom computational units and special data addressing capabilities lead to the design of low power mini-cores. The algorithm suite also consisted of less demanding and/or irregular algorithms (LMS, compression) that required sub-sample rate signal processing justifying the use of a DSP/CPUcore.The thesis also contributes to the recent trend in the development of intellectual property based design methodologies. The actual mini-core designs are parameterized in word-size, memory-size, etc. and can be instantiated according to the needs of the application at hand. They are intended as low power programmable building blocks for a standard cell synthesis based design flow leading to a system-on-chip.Two mini-cores targeting FIR and IIR type of algorithms have been designed to evaluate the concept. Results obtained from the design of a prototype chip demonstrate a power consumption that is only 1.5 -1.6 times larger than commercial hardwired ASICs and more than 6 -21 times lower than current state of the art low-power DSP processors.An orthogonal but practical contribution of this thesis is the test bench implementation. A PCI-based FPGA board has been used to equip a standard desktop PC with tester facilities. The test bench proved to be a viable alternative to conventional expensive test equipment.

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Section: Application/domain-specific Processorsmentioning

confidence: 92%

“…The algorithmic complexity in these systems is growing at a phenomenal pace that the compute power delivered by DSP processors can not follow. Architectures with heterogeneous programmable units are evolving [82,1] to fill the compute power gap to realize such systems.…”

Section: Programmable Dspsmentioning

confidence: 99%

Low-Power Digital Signal Processing

Oklobdzija¹

2001

The Computer Engineering Handbook

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“…However, the demanding energy efficiency constraints of mobile applications prohibit the use of general purpose processors. Instead, the tight efficiency requirements of versatile signal processing systems lead to application specific heterogeneous multiprocessor architectures [29].…”

Section: Architecture Elementsmentioning

confidence: 99%

Heterogeneous MP-SoC

Kogel¹,

Meyr

2004

Proceedings of the 41st Annual Design Automation Conference

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To meet conflicting flexibility, performance and cost constraints of demanding signal processing applications, future designs in this domain will contain an increasing number of application specific programmable units combined with complex communication and memory infrastructures. Novel architecture trends like Application Specific Instruction-set Processors (ASIPs) as well as customized buses and Network-on-Chip based communication promise enormous potential for optimization. However, state-of-the-art tooling and design practice is not in a shape to take advantage of this advances in computer architecture and silicon technology. Currently, EDA industry develops two diverging strategies to cope with the design complexity of such application specific, heterogeneous MP-SoC platforms. First, the IPdriven approach emphasizes the composition of MP-SoC platforms from configurable off-the-shelf Intellectual Property blocks. On the other hand, the design-driven approach strives to take design efficiency to the required level by use of system level design methodologies and IP generation tools. In this paper, we discuss technical and economical aspects of both strategies. Based on the analysis of recent trends in computer architecture and system level design, we envision a hand-in-hand approach of signal processing platform architectures and design metholodgy to conquer the complexity crisis in emerging MP-SoC developments.

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“…It employs four types of execution nodes: scalar (actually a MIPS RISC core), arithmetic, bit manipulation and finite state machine nodes. The Picochip's device features a deterministic high-speed switching matrix linking a heterogeneous array [9] of many hundred programmable 16-bit processors to handle the high-speed chip-rate functions, the lower-speed symbol-rate processing and the control functions in a single structure. In a parallel device, it is important that the granularity of these elements is well aligned to the tasks within a communications system, striking a balance between the very fine granularity of a universal FPGA or the "big chunks" of a powerful DSP.…”

Section: Reconfigurable Architecturesmentioning

confidence: 99%

The picoArray and reconfigurable baseband processing for wireless basestations

Baines¹,

Pulley²

2003

IEE Colloquium on DSP Enabled Radio

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Recently, a number of companies have announced that they are developing new devices for signal processing based on novel architectures. picoChip have recently sampled just such a platform, together with complete toolchain & systems library. This product is based on a massively parallel array of heterogonous processors and delivers extraordinary computational power, eliminating many of the constraints imposed by more traditional architectures. This paper will discuss how parallel architectures can be applied to demanding signal processing systems, and what are the trade-offs with such an approach. It will discuss how such devices can be programmed & how they fit into a traditional development environment. The discussion will be based around the case-study of a real design exercise for a 64 channel 3G (WCDMA) basestation.

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Novel application-specific signal processing architectures for wideband CDMA and TDMA applications

Cited by 14 publications

References 9 publications

Low-Power Digital Signal Processing

Low-Power Digital Signal Processing

Heterogeneous MP-SoC

The picoArray and reconfigurable baseband processing for wireless basestations

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