Novel Approach of Semiconductor Manufacturing Process on Copper Dual Damascene Processes Integration

Abstract

The performance of the manufacturing process in each of these areas determines the overall manufacturability of the process. As device geometries are reduced, understanding and minimising the sources of process-induced defects is critical to achieving and maintaining high device yields. This paper presents a comprehensive investigation of a novel metrology on semiconductor process module integration and technology on optimal integrated lithography processes and solution to the problem of defects reduction on semiconductor wafer in sub-micron processes integration. As dual damascene integration copper process is complicated and critical in semiconductor processes. It has been common knowledge that pattern collapse and missing of this process and numerous defects could be prevented by optimal the process module tuning. To investigate novel semiconductor process integration on deep pattern aspect ratio effects of sub-micron semiconductor wafer BEOL (Back-End-Of-Line) structure were included in this study. Moreover, the electrical device investigations of device checking were also included.

Feasibility Study of Process Integration for High Aspect Ratio Hard-Mask Scheme Technologies of Low-k/Cu Interconnect Fabrication

“…Because the fabrication process of a semiconductor wafer is complicated and there is a tradeoff among module processes, the process-tuning procedures become more complicated. A method of forming optimal dual damascene process for the BEOL process was proposed to overcome these challenges, accurate, and repeatable depth assessment of damascene structures requires the ability to resolve high-aspect-ratio structures in both a high density and isolated structures in the manufacturing processes [10,11].…”