Novel Architecture of Feedforward Second-Order Multibit   AD Modulator

San, Hao; Konagaya, Hajime; Xu, Feng; Motozawa, Atsushi; Kobayashi, Haruo; Ando, Kazumasa; Yoshida, Hiroshi; Murayama, Chieto; Miyazawa, Kanichi

doi:10.1093/ietfec/e91-a.4.965

Cited by 7 publications

(10 citation statements)

References 13 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…We propose here an improved architecture of a noisecoupled ΔΣAD modulator with shared OP-Amp (11) . It extends the OP-Amp sharing technique for feedforward ΔΣAD modulator (12) to the noise-coupled ΔΣAD modulator architecture. Figure 4 shows the block diagram of the proposed ΔΣAD modulator, and it consists of a single DACfeedback, two integrators and a noise injection path.…”

Section: Proposed Noise-coupled δσAd Modulator With Shared Op-ampmentioning

confidence: 99%

“…Figure 5 shows the fully differential switched-capacitor circuit implementation of the proposed ΔΣAD modulator (shown in Fig.4) with shared OP-Amp to realize the signal summation. The implementation circuit without error-feedback path is the same as the realization of the 2nd-order ΔΣAD modulator (12) . Parasitic-insensitive switched-capacitor structures are used for integrators (13) , and negative capacitors in the modulator are easily implemented by changing the polarity of input signals in the fully differential circuit.…”

Section: Proposed δσAd Modulator Architecturementioning

confidence: 99%

See 1 more Smart Citation

Noise-Coupled .DELTA..SIGMA.AD Modulator with Shared OP-Amp

et al. 2009

View full text Add to dashboard Cite

This paper proposes an improved architecture of the noise-coupled ΔΣAD modulator with OP-Amp sharing technique. The noise-coupled ΔΣAD modulator enhances the order of noise-shaping efficiently by adding some passive capacitors and switches. However, in a conventional noise-coupled ΔΣAD modulator with feedforward path, an analog adder is needed before the quantizer, and especially in a multibit modulator, an additional amplifier is necessary to realize the summation of feedforward signals and coupled quantization noise, which leads to extra chip area and power dissipation. In this paper, we propose a novel architecture of the noise-coupled ΔΣAD modulator with OP-Amp sharing technique, which realizes the summation of feedforward signals and coupled quantization noise without an additional amplifier. The proposed architecture is functionally equivalent to the conventional noise-coupled modulator with smaller chip area and low power dissipation. We have performed simulation with MATLAB and SPICE to verify the effectiveness of the proposed architecture and modulator circuits. The simulation results show that the proposed modulator can realize the noise-shaping enhancement effectually as the same as the conventional noise-coupled modulator with small overhead.

show abstract

Section: Proposed Noise-coupled δσAd Modulator With Shared Op-ampmentioning

confidence: 99%

Section: Proposed δσAd Modulator Architecturementioning

confidence: 99%

Noise-Coupled .DELTA..SIGMA.AD Modulator with Shared OP-Amp

et al. 2009

View full text Add to dashboard Cite

show abstract

“…To avoid the use of an extra active adder, i.e. an extra opamp, for a low-distortion DSM, earlier studies [8], [9] remove the summing node from the quantizer input to the last integrator input. Other works [1], [10] respectively propose an integrator structure which can use an opamp to obtain a secondorder shaping ability as the function of two cascade integrators.…”

Section: Introductionmentioning

confidence: 99%

A Single Opamp Third-Order Low-Distortion Delta-Sigma Modulator with SAR Quantizer Embedded Passive Adder

Chao

Hou

Liu

et al. 2014

IEICE Trans. Electron.

View full text Add to dashboard Cite

A third-order low-distortion delta-sigma modulator (DSM), whose third-order noise-shaping ability is achieved by just a single opamp, is proposed. Since only one amplifier is required in the whole circuit, the designed DSM is very power efficient. To realize the adder in front of quantizer without employing the huge-power opamp, a capacitive passive adder, which is the digital-to-analog converter (DAC) array of a successive-approximation-type quantizer, is used. In addition, the feedback path timing is extended from a nonoverlapping interval for the conventional low-distortion structure to half of the clock period, so that the strict operation timing issue with regard to quantization and the dynamic element matching (DEM) logic operation can be solved. In the proposed DSM structure, the features of the unity-gain signal transfer function (STF) and finite-impulse-response (FIR) noise transfer function (NTF) are still preserved, and thus advantages such as a relaxed opamp slew rate and reduced output swing are also maintained, as with the conventional low-distortion DSM. Moreover, the memory effect in the proposed DSM is analyzed when employing the opamp sharing for integrators. The proposed third-order DSM with a 4-bit SAR ADC as the quantizer is implemented in a 90-nm CMOS process. The post-layout simulations show a 79.8-dB signal-to-noise and distortion ratio (SNDR) in the 1.875-MHz signal bandwidth (OSR=16). The active area of the circuit is 0.35 mm 2 and total power consumption is 2.85 mW, resulting in a figure of merit (FOM) of 95 fJ/conversion-step.

show abstract

“…Substituting equations ( 4) and (5) by equation (3), the loop output is determined as: (6) Where: x(z) is input signal, STF (Signal Transfer Function) = 1 − z , y(z) is output signal and q(z) is quantization noise of the converter, as shown in fig. (1b).…”

mentioning

confidence: 99%

A Second-Order Single Loop Oversampling Analog-to-Digital Converter (ADC) with Proposed Hybrid Feedforward/Feedback Architecture

Azzawi¹

2012

ETJ

View full text Add to dashboard Cite

This paper proposes hybrid architecture of feedforward/feedback second order single-loop modulator for high resolution analog-to-digital converter (ADC) applications. Different techniques for oversampling modulator are discussed. The proposed architecture consists of three stages. The first stage is nd 2 order single loop oversampling ADC with novel feedforward/feedback architecture. In the second stage, an error cancellation circuit (ECC) is proposed at the output of the modulator to noise shaping of quantization noise. In addition, the third stage is a decimation filter in order to reduce the oversampling ratio (OSR) which is suitable for broadband applications. With low OSR=24, the signal-to-noise ratio (SNR) is improved about 55 dB if compared with traditional architecture (feedback singleloop high order topology). The achieved resolution or the effective number of bits (ENOB) is (22-bit). With high OSR=256, the net improvement in quantization noise reduction is 64 dB if compared with feedforward architecture (single-loop high order) and the ENOB=28. Finally a 1-bit quantizer is used in the proposed architecture which greatly decreases the circuit implementation complexity and power consumption. Simulation results show the superiority performance of proposed hybrid architecture as compared with traditional modulator topologies (feedforward and feedback).

show abstract

Novel Architecture of Feedforward Second-Order Multibit AD Modulator

Cited by 7 publications

References 13 publications

Noise-Coupled .DELTA..SIGMA.AD Modulator with Shared OP-Amp

Noise-Coupled .DELTA..SIGMA.AD Modulator with Shared OP-Amp

A Single Opamp Third-Order Low-Distortion Delta-Sigma Modulator with SAR Quantizer Embedded Passive Adder

A Second-Order Single Loop Oversampling Analog-to-Digital Converter (ADC) with Proposed Hybrid Feedforward/Feedback Architecture

Contact Info

Product

Resources

About