Novel Arithmetics to Accelerate Machine Learning Classifiers in Autonomous Driving Applications

Cococcioni, Marco; Rossi, Federico; Ruffaldi, Emanuele; Saponara, Sergio

doi:10.1109/icecs46596.2019.8965031

Cited by 10 publications

(10 citation statements)

References 14 publications

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“…The posit format [11,12,16,19] is a configurable fixed length format for real number representation; the format configuration involves the number of overall bits (nbits) and the maximum number of exponent bits (esbits).…”

Section: Posit Arithmeticmentioning

confidence: 99%

“…Another very promising alternative to IEEE 32-bit Floating-point standard is the posit TM number system, proposed by Gustafson [19]. This format has been proven to match single precision accuracy performance with only 16 bits used for the representation [9,12,16,17,24]. Furthermore, the first hardware implementations of this novel type are very promising in terms of energy consumption and area occupation [10,20,28].…”

Section: Introductionmentioning

confidence: 99%

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Vectorizing posit operations on RISC-V for faster deep neural networks: experiments and comparison with ARM SVE

Cococcioni

Rossi

Ruffaldi³

et al. 2021

Neural Comput & Applic

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With the arrival of the open-source RISC-V processor architecture, there is the chance to rethink Deep Neural Networks (DNNs) and information representation and processing. In this work, we will exploit the following ideas: i) reduce the number of bits needed to represent the weights of the DNNs using our recent findings and implementation of the posit number system, ii) exploit RISC-V vectorization as much as possible to speed up the format encoding/decoding, the evaluation of activations functions (using only arithmetic and logic operations, exploiting approximated formulas) and the computation of core DNNs matrix-vector operations. The comparison with the well-established architecture ARM Scalable Vector Extension is natural and challenging due to its closedness and mature nature. The results show how it is possible to vectorize posit operations on RISC-V, gaining a substantial speed-up on all the operations involved. Furthermore, the experimental outcomes highlight how the new architecture can catch up, in terms of performance, with the more mature ARM architecture. Towards this end, the present study is important because it anticipates the results that we expect to achieve when we will have an open RISC-V hardware co-processor capable to operate natively with posits.

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Section: Posit Arithmeticmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Vectorizing posit operations on RISC-V for faster deep neural networks: experiments and comparison with ARM SVE

Cococcioni

Rossi

Ruffaldi³

et al. 2021

Neural Comput & Applic

Self Cite

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show abstract

“…The Posit format has been introduced by John L. Gustafson in Reference [8] and was further investigated in Reference [9,10,12]. The format is a fixed-length one with up to 4 fields as also reported in Figure 1: Given a Posit on nbits; esbits, represented by the integer X, and e and f respectively as the exponent and fraction values, the real number r represented by that encoding is as follows:…”

Section: Posit Arithmeticmentioning

confidence: 99%

“…For this paper, we employ our software implementation of Posit numbers developed at the University of Pisa, called cppPosit. As already described in References [9,12], the library classifies Posit operations into four different classes (from L1 to L4), with increasing computational complexity.…”

Section: Cppposit Librarymentioning

confidence: 99%

“…Other formats also come from the concept of transprecision computing [6,7] (NVIDIA Turing architectures allow computation with 4-, 8-, and 32-bit integers and with 16-and 32-bit floats). The up-and-coming Posit format has been theoretically [8][9][10] and practically [11] proven to be a perfect replacement for IEEE float numbers when applied to DNNs in terms of efficiency and accuracy.…”

Section: Introductionmentioning

confidence: 99%

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Fast Approximations of Activation Functions in Deep Neural Networks when using Posit Arithmetic

Cococcioni

Rossi

Ruffaldi³

et al. 2020

Sensors

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With increasing real-time constraints being put on the use of Deep Neural Networks (DNNs) by real-time scenarios, there is the need to review information representation. A very challenging path is to employ an encoding that allows a fast processing and hardware-friendly representation of information. Among the proposed alternatives to the IEEE 754 standard regarding floating point representation of real numbers, the recently introduced Posit format has been theoretically proven to be really promising in satisfying the mentioned requirements. However, with the absence of proper hardware support for this novel type, this evaluation can be conducted only through a software emulation. While waiting for the widespread availability of the Posit Processing Units (the equivalent of the Floating Point Unit (FPU)), we can already exploit the Posit representation and the currently available Arithmetic-Logic Unit (ALU) to speed up DNNs by manipulating the low-level bit string representations of Posits. As a first step, in this paper, we present new arithmetic properties of the Posit number system with a focus on the configuration with 0 exponent bits. In particular, we propose a new class of Posit operators called L1 operators, which consists of fast and approximated versions of existing arithmetic operations or functions (e.g., hyperbolic tangent (TANH) and extended linear unit (ELU)) only using integer arithmetic. These operators introduce very interesting properties and results: (i) faster evaluation than the exact counterpart with a negligible accuracy degradation; (ii) an efficient ALU emulation of a number of Posits operations; and (iii) the possibility to vectorize operations in Posits, using existing ALU vectorized operations (such as the scalable vector extension of ARM CPUs or advanced vector extensions on Intel CPUs). As a second step, we test the proposed activation function on Posit-based DNNs, showing how 16-bit down to 10-bit Posits represent an exact replacement for 32-bit floats while 8-bit Posits could be an interesting alternative to 32-bit floats since their performances are a bit lower but their high speed and low storage properties are very appealing (leading to a lower bandwidth demand and more cache-friendly code). Finally, we point out how small Posits (i.e., up to 14 bits long) are very interesting while PPUs become widespread, since Posit operations can be tabulated in a very efficient way (see details in the text).

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Posits and the state of numerical representations in the age of exascale and edge computing

2021

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Growing constraints on memory utilization, power consumption, and I/O throughput have increasingly become limiting factors to the advancement of high performance computing (HPC) and edge computing applications. IEEE-754 floating-point types have been the de facto standard for floating-point number systems for decades, but the drawbacks of this numerical representation leave much to be desired. Alternative representations are gaining traction, both in HPC and machine learning environments. Posits have recently been proposed as a drop-in replacement for the IEEE-754 floating-point representation. We survey the state-of-the-art and state-of-the-practice in the development and use of posits in edge computing and HPC. The current literature supports posits as a promising alternative to traditional floating-point systems, both as a stand-alone replacement and in a mixed-precision environment. Development and standardization of the posit type is ongoing, and much research remains to explore the application of posits in different domains, how to best implement them in hardware, and where they fit with other numerical representations.

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Novel Arithmetics to Accelerate Machine Learning Classifiers in Autonomous Driving Applications

Cited by 10 publications

References 14 publications

Vectorizing posit operations on RISC-V for faster deep neural networks: experiments and comparison with ARM SVE

Vectorizing posit operations on RISC-V for faster deep neural networks: experiments and comparison with ARM SVE

Fast Approximations of Activation Functions in Deep Neural Networks when using Posit Arithmetic

Posits and the state of numerical representations in the age of exascale and edge computing

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