Novel at-Design-Rule Via-to-Metal Overlay Metrology for 193-nm Lithography

ABSTRUCTPattern placement error (PPE) of device pattern and overlay mark does not necessarily coincide. So it is important to measure PPE of device pattern accurately for optimizing overlay mark design. But it has been hard. To resolve this problem a new method has been developed. As a device pattern via chain pattern is used that consists of 1 st metal, via, and 2 nd metal layers. The electrical resistance is almost determined by the contact area of metal and via which depend on their mutual overlay. Since the resistance is inversely proportional to the contact area, the resistance changes sharply as the overlay error becomes large. With the characteristic the fine measurement accuracy of about 1nm has been gotten. We evaluate the relation of PPE between the device pattern and various types of overlay marks such as box in box mark and device size-segmented mark on 65nm node Cu interconnect. As a result, it has been confirmed that the device sizesegmented mark most represents the PPE of device pattern at various aberrations.

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“…So it is crucial to measure PPE of device pattern precisely and compare it to PPE of overlay mark. [2] [3] …”

Section: Introductionmentioning

confidence: 99%

Study of segmented overlay mark fidelity based on electrical property of device

Minami¹,

Yabe²,

Nasuno³

et al. 2005

SPIE Proceedings

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“…2). § Aberration-induced error 8 . A scanner lens may image the mark and small device features differently ( Fig.…”

Section: The Overlay Control Problemmentioning

confidence: 99%

Microeconomic of overlay control at the 65 nm technology node

Allgair¹,

Monahan²

2003 5th International Conference on ASIC. Proceedings (IEEE Cat. No.03TH8690)

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ITRS working groups have identified overlay control as a technology roadblock with no known solutions at the 65nm node and beyond. The most serious problems are total measurement uncertainty, CMP process robustness, and device correlation. A systematic root-cause analysis of pattern placement error (PPE) at Motorola's Dan Noble Center has determined that current box-in-box overlay targets cause deficiencies in all three categories. A proposed solution utilizes advanced imaging targets that are grating-based and can be segmented with features that are similar to those in the device. In the case of poly-to-STI overlay using 193nm lithography tools, these targets show a 40% decrease in total measurement uncertainty.

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