Novel BCD adders and their reversible logic implementation for IEEE 754r format

Abstract

IEEE 754r is the ongoing revision to the IEEE 754 floating point standard and a major enhancement to the standard is the addition of decimal format. This paper proposes two novel BCD adders called carry skip and carry look-ahead BCD adders respectively. Furthermore, in the recent years, reversible logic has emerged as a promising technology having its applications in low power CMOS, quantum computing, nanotechnology, and optical computing. It is not possible to realize quantum computing without reversible logic. Thus, this paper also paper provides the reversible logic implementation of the conventional BCD adder as the well as the proposed Carry Skip BCD adder using a recently proposed TSG gate. Furthermore, a new reversible gate called TS-3 is also being proposed and it has been shown that the proposed reversible logic implementation of the BCD Adders is much better compared to recently proposed one, in terms of number of reversible gates used and garbage outputs produced. The reversible BCD circuits designed and proposed here form the basis of the decimal ALU of a primitive quantum CPU.

Design of Optimal Carry Skip Adder and Carry Skip BCD Adder Using Reversible Logic Gates

“…(Biswas et al, 2008b) 15 14 11 (Thapliyal et al, 2006) 15 27 13 (Islam et al, 2009;15 14 11 Biswas et al, 2008b) (Islam and Begam, 2008) …”

“…This MTSG gate in Fig. 3 can be used to realize a full adder by providing constant '0' at the input D.Quantum cost of reversible MTSG gate is 6 which is lower than 13 of TSG gate (Thapliyal et al, 2006). This gate is used in the design so as to produce the sum, carry and the propagate output of the inputs.…”

Quantum Cost Efficient Reversible BCD Adder for Nanotechnology Based Systems

“…The design presented in [16] requires 23 reversible gates and the design given in [17] requires 16 and 22 reversible gates (carry skip BCD adder) respectively.…”

Scope of Reversible Engineering at Gate-Level : Fault - Tolerant Combinational Adders

“…A 3*3 Double Feynman gate [18] [3] .The input vector is I (A, B, C) and the output vector is O (P, Q, R). The outputs are defined as …”