Novel binary linear programming for high performance clock mesh synthesis

Cho, Minsik; Pan, David Z.; Puri, Ruchir

doi:10.1109/iccad.2010.5653737

Cited by 13 publications

(13 citation statements)

References 18 publications

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“…An obstacle-avoiding clock mesh synthesis method which applies a two-stage approach of mesh construction followed by driving-tree synthesis is proposed in [21], [26]. A methodology based on binary linear programming for clock mesh synthesis is described in [5].…”

Section: Meshesmentioning

confidence: 99%

Multilevel tree fusion for robust clock networks

Lee¹

2011

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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Abstract-Recent improvements in clock-tree and mesh-based topologies maintain a healthy competition between the two. Trees require much smaller capacitance, but meshes are naturally robust against process variation and can accommodate late design changes. Cross-link insertion has been advocated to make trees more robust, but is limited in practice to short distances. In this work we develop a novel non-tree topology that fuses several clock trees to create large-scale redundancy in a clock network. Empirical validation shows that our novel clock-network structure incrementally enhances robustness to satisfy given variation constraints. Our implementation called Contango3.0 produces robust clock networks even for challenging skew limits, without parallel buffering used by other implementations. It also offers a fine trade-off between power and robustness, increasing the capacitance of the initial tree by less than 60%, which results in 2.3× greater power efficiency than mesh structures.

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Section: Meshesmentioning

confidence: 99%

Multilevel tree fusion for robust clock networks

Lee¹

2011

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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“…In order to reduce the power consumption on the clock mesh, the proposed methods in [1][2][3][4][5][6][7] reduce the mesh grid wirelength and the stub wirelength. The method proposed in this paper reduces the stub wirelength and the switching factor by register clustering, steiner tree-like stub wire connections and clock gating, which reduce the total switching capacitance.…”

Section: A Switching Capacitance On the Mesh Networkmentioning

confidence: 99%

“…Despite providing low skew synchronization, the clock mesh network suffers from high power dissipation due to the redundant grid wires and the short circuit power. Existing methods aim to reduce the power dissipation by reducing the routing wires in the clock mesh such as grid wires and stub wires [1][2][3][4][5][6][7].…”

Section: Introductionmentioning

confidence: 99%

Clock mesh synthesis with gated local trees and activity driven register clustering

Mao

Taşkın

2012

Proceedings of the International Conference on Computer-Aided Design

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A clock mesh network synthesis method is proposed which enables clock gating on the local sub-trees in order to reduce the clock power dissipation. Clock gating is performed with a register clustering strategy that considers both i) the similarity of switching activities between registers in a local area and ii) the timing slack on every local data path in the design. This is the first work known in literature that encapsulates the efficient implementation of the gated local trees and activity driven register clustering with timing slack awareness for clock mesh synthesis. Experimental results show that with gated local tree and activity driven register clustering, the switching capacitance on the mesh network can be reduced by 22% with limited skew degradation. The proposed method has two synthesis modes as low power mode and high performance mode to serve different design purposes.

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“…Obstacle-avoiding clock mesh synthesis in [28], [32] applies a two-stage approach -mesh construction followed by driving-tree synthesis. A clock-mesh synthesis methodology based on binary linear programming is described in [6].…”

Section: Meshes and Cross-linksmentioning

confidence: 99%

Algorithmic tuning of clock trees and derived non-tree structures

Lee¹

2011

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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Abstract-This mini-tutorial covers recent research on clocknetwork tuning. It starts with SPICE-accurate optimizations used in winning entries at the ISPD 2009 and 2010 clock-network synthesis contests. After comparing clock trees to meshes, it outlines a recent redundant clock-network topology that retains most advantages of clock trees, but improves robustness to PVT variations. It also shows how to incorporate clock-network synthesis into global placement to reduce dynamic power and insertion delay.I. INTRODUCTION Clock-network synthesis significantly impacts the performance, area and power dissipation of an integrated circuit, and this impact is aggravated when architectural-level pipelining increases the number of clocked elements [35]. Being responsible for 30-50% of chip power [9], clock networks require careful optimization. Such optimization may require SPICEaccurate timing analysis, otherwise it is difficult to account for the explosion of technology parameters that characterize each advanced technology node. Unfortunately, runtime overhead limits such analysis to only several invocations during optimization. Recent research reviewed in this paper developed comprehensive SPICE-accurate clock-network optimizations subject to capacitance and slew constraints, and cognizant of runtime limitations. The ISPD 2009 and 2010 Clock-Network Synthesis contests organized by IBM Research and Intel Research evaluated these techniques on industry benchmarks. The second contest increased the realism in modeling and evaluation of clock networks, adding the impact of variations and using local rather than global clock skew -a more meaningful parameter for large circuits [10].The growing impact of process, voltage and temperature (PVT) variation complicates the design of reliable clock networks [26], as nominal-parameter optimizations (single corner, no variation) do not ensure high yield. Robustness to variations requires increased power and careful trade-offs. Mesh/grid structures exhibit greater robustness but consume much more power and complicate clock gating. This paper surveys recent clock-network topologies that offer the path-redundancy of meshes, but retain the advantages of clock trees.Clock networks can also be improved by careful positioning of latches and flip-flops. Leaf-level register clustering [3] after global placement can help sharing inverters between flip-flops and reduce clock-network capacitance. In this paper, we review a recent, more general optimization [17] that differentiates sequential elements during global placement and optimizes total dynamic power of signal nets and the clock network.

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Novel binary linear programming for high performance clock mesh synthesis

Cited by 13 publications

References 18 publications

Multilevel tree fusion for robust clock networks

Multilevel tree fusion for robust clock networks

Clock mesh synthesis with gated local trees and activity driven register clustering

Algorithmic tuning of clock trees and derived non-tree structures

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