Novel Bypass Attack and BDD-based Tradeoff Analysis Against All Known Logic Locking Attacks

Xu, Xiaolin; Shakya, Bicky; Tehranipoor, Mark; Forte, Domenic

doi:10.1007/978-3-319-66787-4_10

Cited by 123 publications

(62 citation statements)

References 14 publications

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“…Comparison with functional obfuscation: Xu et al [22] proposed binary decision diagram (BDD)-based obfuscation which operates at the functional level, in contrast to other approaches working at the netlist level. It was shown that their scheme can be tailored to remain resilient against SATbased attacks as well "removal attacks" [22], [23]. As above, we evaluate two approaches of [22] at layout level, namely random obfuscation and Anti-SAT-inspired obfuscation [59].…”

Section: Table VII Area (A) Power (P) and Delay (D) For Full-chip Cmentioning

confidence: 99%

Obfuscating the Interconnects: Low-Cost and Resilient Full-Chip Layout Camouflaging

Patnaik¹,

Ashraf²,

Knechtel³

et al. 2020

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Layout camouflaging can protect the intellectual property of modern circuits. Most prior art, however, incurs excessive layout overheads and necessitates customization of active-device manufacturing processes, i.e., the front-end-of-line (FEOL). As a result, camouflaging has typically been applied selectively, which can ultimately undermine its resilience. Here, we propose a low-cost and generic scheme-full-chip camouflaging can be finally realized without reservations. Our scheme is based on obfuscating the interconnects, i.e., the back-end-ofline (BEOL), through design-time handling for real and dummy wires and vias. To that end, we implement custom, BEOL-centric obfuscation cells, and develop a CAD flow using industrial tools. Our scheme can be applied to any design and technology node without FEOL-level modifications. Considering its BEOL-centric nature, we advocate applying our scheme in conjunction with split manufacturing, to furthermore protect against untrusted fabs. We evaluate our scheme for various designs at the physical, DRC-clean layout level. Our scheme incurs a significantly lower cost than most of the prior art. Notably, for fully camouflaged layouts, we observe average power, performance, and area overheads of 24.96%, 19.06%, and 32.55%, respectively. We conduct a thorough security study addressing the threats (attacks) related to untrustworthy FEOL fabs (proximity attacks) and malicious end-users (SAT-based attacks). An empirical key finding is that only large-scale camouflaging schemes like ours are practically secure against powerful SAT-based attacks. Another key finding is that our scheme hinders both placement-and routing-centric proximity attacks; correct connections are reduced by 7.47X, and complexity is increased by 24.15X, respectively, for such attacks.

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Section: Table VII Area (A) Power (P) and Delay (D) For Full-chip Cmentioning

confidence: 99%

Obfuscating the Interconnects: Low-Cost and Resilient Full-Chip Layout Camouflaging

Patnaik¹,

Ashraf²,

Knechtel³

et al. 2020

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…These works seek to impose exponential computation complexity for the SAT solver. Still, most of these techniques are vulnerable to some degree when subject to tailored attacks such as [53]- [55]. Besides, we note that prior art on SAT attacks tender exclusively to deterministic computing and circuits.…”

Section: Hardware Securitymentioning

confidence: 99%

Spin-Orbit Torque Devices for Hardware Security: From Deterministic to Probabilistic Regime

Patnaik

Rangarajan

Knechtel³

et al. 2020

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Protecting intellectual property (IP) has become a serious challenge for chip designers. Most countermeasures are tailored for CMOS integration and tend to incur excessive overheads, resulting from additional circuitry or device-level modifications. On the other hand, power density is a critical concern for sub-50 nm nodes, necessitating alternate design concepts. Although initially tailored for error-tolerant applications, imprecise computing has gained traction as a general-purpose design technique. Emerging devices are currently being explored to implement ultra-low-power circuits for inexact computing applications. In this paper, we quantify the security threats of imprecise computing using emerging devices. More specifically, we leverage the innate polymorphism and tunable stochastic behavior of spin-orbit torque (SOT) devices, particularly, the giant spin-Hall effect (GSHE) switch. We enable IP protection (by means of logic locking and camouflaging) simultaneously for deterministic and probabilistic computing, directly at the GSHE device level. We conduct a comprehensive security analysis using state-of-the-art Boolean satisfiability (SAT) attacks; this study demonstrates the superior resilience of our GSHE primitive when tailored for deterministic computing. We also demonstrate how probabilistic computing can thwart most, if not all, existing SAT attacks. Based on this finding, we propose an attack scheme called probabilistic SAT (PSAT) which can bypass the defense offered by logic locking and camouflaging for imprecise computing schemes. Further, we illustrate how careful application of our GSHE primitive can remain secure even on the application of the PSAT attack. Finally, we also discuss side-channel attacks and invasive monitoring, which are arguably even more concerning threats than SAT attacks.

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“…involves the expression of combinational logic in the form of BDDs and embedding of the locking mechanism at the BDD level [26,45]. BDDs are canonical expressions for Boolean logic, represented in the form of a directed acyclic graph (DAG) with arcs, nodes, and leaves.…”

Section: -Binary Decision Diagram (Bdd): Another Techniquementioning

confidence: 99%

“…Many attacks have been proposed to break combinational obfuscation and retrieve the key [22,38,41,45,48]. Secure obfuscation techniques should ideally force the attacker to brute force the key.…”

Section: Attacksmentioning

confidence: 99%

Development and Evaluation of Hardware Obfuscation Benchmarks

Amir

Shakya

et al. 2018

J Hardw Syst Secur

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Obfuscation is a promising solution for securing hardware intellectual property (IP) against various attacks, such as reverse engineering, piracy, and tampering. Due to the lack of standard benchmarks, proposed techniques by researchers and practitioners in the community are evaluated by existing benchmark suites such as ISCAS-85, ISCAS-89, and ITC-99. These open source benchmarks, though widely utilized, are not necessarily suitable for the purpose of evaluating hardware obfuscation techniques. In this context, we believe that it is important to establish a set of well-defined benchmarks, on which the effectiveness of new and existing obfuscation techniques and attacks on them can be compared. In this paper, we describe a set of such benchmarks obfuscated with some popular methods that we created to facilitate this need. These benchmarks have been made publicly available on Trust-Hub web portal. Moreover, we provide the first evaluation of several obfuscation approaches based on the metrics and existing attacks using this new suite. Finally, we discuss our observations and guidance for future work in hardware obfuscation and benchmarking. Keywords Hardware obfuscation • Benchmark development • Benchmark testing • Hardware security 1 Introduction With the rising costs of chip fabrication at advanced technology nodes and ever-increasing design complexity, today's semiconductor industry has shifted to a predominantly fabless business model. In this model, a design house typically sources pre-designed and pre-verified hardware IPs from different sources including third party IP (3PIP) vendors, integrates them into a system-on-chip (SoC), and ships the

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Novel Bypass Attack and BDD-based Tradeoff Analysis Against All Known Logic Locking Attacks

Cited by 123 publications

References 14 publications

Obfuscating the Interconnects: Low-Cost and Resilient Full-Chip Layout Camouflaging

Obfuscating the Interconnects: Low-Cost and Resilient Full-Chip Layout Camouflaging

Spin-Orbit Torque Devices for Hardware Security: From Deterministic to Probabilistic Regime

Development and Evaluation of Hardware Obfuscation Benchmarks

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