Novel CMOS static ternary logic using double pass-transistor logic

Hang, Guoqiang; Zhou, Xin

doi:10.1109/icise.2010.5689867

Cited by 7 publications

(4 citation statements)

References 12 publications

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“…Otherwise, with clk=0, the ternary latch remains unchanged. Two cascaded ternary latches can be used to construct a Dtype master/slave ternary flip-flop with edge-triggered characteristic as depicted in Fig.6 [16]. Its behavior is straightforward.…”

Section: Neuron-mos Inverter and Ternary Literal Circuitmentioning

confidence: 99%

“…The above analysis shows that the circuit properly operates as a static ternary inverter/identity cell without static power consumption. The use of constant sources (2,1,0) rather than variable signal sources makes the circuit realize level-restored outputs [16]. In the design of ternary digital systems, flip-flops are the fundamental building blocks.…”

Section: Neuron-mos Inverter and Ternary Literal Circuitmentioning

confidence: 99%

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Design of ternary D flip-flop using one latch with neuron-MOS literal circuit

Zhou

Hang

2013

2013 Ninth International Conference on Natural Computation (ICNC)

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A new ternary D flip-flop using one latch is presented. In order to meet the non-transparent demand in flip-flops, the narrow pulses produced by the race-hazard of the clock signal are used to control the latch. In the proposed design scheme, literal functions are realized by using neuron-MOS transistors. Then, the pass transistors used to pass ternary signal are controlled by the outputs of the literal circuit to realize ternary inverter and identity cell. As the variable threshold voltage can be achieved easily in neuron-MOS literal circuit, the proposed ternary circuit has simple structure. Compared to the traditional voltage-mode MVL flip-flops, the proposed ternary flip-flop can be fabricated by standard CMOS process with a double-ploy layer, without multi-level ion implantation applied in the conventional voltage-mode multiple-valued circuits. HSPICE simulation results using TSMC 0.35μm double-poly 4-metal CMOS process parameters have verified the characteristics of the proposed scheme. The proposed construction can be easily extended to the design of multiple-valued edge-triggered flip-flop with a higher radix.

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Section: Neuron-mos Inverter and Ternary Literal Circuitmentioning

confidence: 99%

Section: Neuron-mos Inverter and Ternary Literal Circuitmentioning

confidence: 99%

Design of ternary D flip-flop using one latch with neuron-MOS literal circuit

Zhou

Hang

2013

2013 Ninth International Conference on Natural Computation (ICNC)

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“…The high-threshold and low-threshold comparative operations of switch signal theory [11] are introduced first to de-work rhythm of the other two power clocks Φ 1 and Φ, the input sampled values and the CMOS-latch structure are used to finish charging the output loads and recovering the charge on the output loads. Φ 1 and Φ have the same phase but different amplitudes: the amplitude values of Φ 1 and Φ are V DD /2 and V DD , which correspond to logic 1 and logic 2 respectively; their phase difference with Φ is 180 • (the output phase is the same as Φ 1 and Φ).…”

Section: Switch-signal Theory and The Theory Of Three Essential Elementsmentioning

confidence: 99%

“…Figure 5 gives a transient energy consumption comparison between the DTCTGAL and ternary DPL [11] (double passtransistor logic) circuits, where the input in is "210210. . .…”

Section: Computer Simulation and Conclusionmentioning

confidence: 99%

Design of a DTCTGAL circuit and its application

Wang¹,

Li²,

Mei

2009

J. Semicond.

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By research on the switch-signal theory for multiple-valued logic circuits, the theory of three essential elements and the principle of adiabatic circuits, a design scheme for a double power clock ternary clocked transmission gate adiabatic logic (DTCTGAL) circuit is presented. The energy injection and recovery can be conducted by the bootstrapped NMOSFET, which makes the circuit maintain the characteristics of energy recovery as well as multiple-valued input and output. An XOR/XNOR circuit based on DTCTGAL is also presented using this design scheme. Finally, using the parameters of a TSMC 0.25 μm CMOS device, PSPICE simulation results indicate that the proposed circuits have correct logic and significant low power characteristics.

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DPL-Based Novel 1-Trit Ternary Half-Subtractor

Raj

Singh

et al. 2019

Lecture Notes in Electrical Engineering

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Novel CMOS static ternary logic using double pass-transistor logic

Cited by 7 publications

References 12 publications

Design of ternary D flip-flop using one latch with neuron-MOS literal circuit

Design of ternary D flip-flop using one latch with neuron-MOS literal circuit

Design of a DTCTGAL circuit and its application

DPL-Based Novel 1-Trit Ternary Half-Subtractor

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