Novel Code Converter Employing Reversible Logic

Saligram, Rakshith; Rakshith, T. R.

doi:10.5120/8303-1759

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) Peres Gate1

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2013

2021

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Cited by 14 publications

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“…Peres gate which is a 3*3 gate having inputs (A, B, C) and outputs P = A; Q = A XOR B; R = AB XOR C. It has Quantum cost four [19].…”

Section: ) Peres Gatementioning

confidence: 99%

Reversible Multiplier with Peres Gate and Full Adder

Morankar¹,

Sakode²

2014

IOSRJECE

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Low Power dissipation and smaller area are one of the important factors while designing multipliers for digital circuits. As multipliers used in digital circuits dissipate large amount of heat whenever there is a transition of bits. Reversible Logic has emerged as a promising technology in reducing power dissipation. It has application in various fields such as low power VLSI, Quantum computing and Nano-technology. Hence, In this paper we try to design a reversible multiplier using Peres gate and Full adder. We show that, proposed multiplier is efficient in terms area, power and delay. Furthermore, it requires fewer garbage outputs and constant inputs. Proposed reversible multiplier is implemented using VHDL, simulated and synthesized on Xilinx 13.1 tool.

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“…Peres gate which is a 3*3 gate having inputs (A, B, C) and outputs P = A; Q = A XOR B; R = AB XOR C. It has Quantum cost four [19].…”

Section: ) Peres Gatementioning

confidence: 99%